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HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
Data Sheet June 1, 2006 FN4659.13
Low Power UniSLIC14 Family
The UniSLIC14 is a family of Ultra Low Power SLICs. The feature set and common pinouts of the UniSLIC14 family positions it as a universal solution for: Plain Old Telephone Service (POTS), PBX, Central Office, Loop Carrier, Fiber in the Loop, ISDN-TA and NT1+, Pairgain and Wireless Local Loop. The UniSLIC14 family achieves its ultra low power operation through: Its automatic single and dual battery selection (based on line length) and battery tracking anti clipping to ensure the maximum loop coverage on the lowest battery voltage. This architecture is ideal for power critical applications such as ISDN NT1+, Pairgain and Wireless local loop products. The UniSLIC14 family has many user programmable features. This family of SLICs delivers a low noise, low component count solution for Central Office and Loop Carrier universal voice grade designs. The product family integrates advanced pulse metering, test and signaling capabilities, and zero crossing ring control. The UniSLIC14 family is designed in the Intersil "Latch" free Bonded Wafer process. This process dielectrically isolates the active circuitry to eliminate any leakage paths as found in our competition's JI process. This makes the UniSLIC14 family compliant with "hot plug" requirements and operation in harsh outdoor environments.
Features
* Ultra Low Active Power (OHT) < 60mW * Single/Dual Battery Operation * Automatic Silent Battery Selection * Power Management/Shutdown * Battery Tracking Anti Clipping * Single 5V Supply with 3V Compatible Logic * Zero Crossing Ring Control - Zero Voltage On/Zero Current Off * Tip/Ring Disconnect * Pulse Metering Capability * 4 Wire Loopback * Programmable Current Feed * Programmable Resistive Feed * Programmable Loop Detect Threshold * Programmable On-Hook and Off-Hook Overheads * Programmable Overhead for Pulse Metering * Programmable Polarity Reversal Time * Selectable Transmit Gain 0dB/-6dB * 2 Wire Impedance Set by Single Network * Loop and Ground Key Detectors * On-Hook Transmission * Common Pinout * Pb-Free Plus Anneal Available (RoHS Compliant) * HC55121 - Polarity Reversal * HC55130 - -63dB Longitudinal Balance * HC55140 - Polarity Reversal - Ground Start - Line Voltage Measurement - 2 Wire Loopback - -63dB Longitudinal Balance * HC55142 - Polarity Reversal - Ground Start - Line Voltage Measurement - 2.2VRMS Pulse Metering - 2 Wire Loopback * HC55150 - Polarity Reversal - Line Voltage Measurement - 2.2VRMS Pulse Metering - 2 Wire Loopback
Block Diagram
RRLY TRLY1 TRLY2 DT DR ZERO CURRENT CROSSING RING TRIP DETECTOR POLARITY REVERSAL RING AND TEST RELAY DRIVERS STATE DECODER AND DETECTOR LOGIC LOOP CURRENT DETECTOR GKD/LOOP LENGTH DETECTOR C1 C2 C3 C4 C5 SHD GKD_LVM CRT_REV_LVM ILIM RSYNC_REV ROH CDC RDC_RAC RD VTX VRX PTG ZT CH
TIP RING BGND AGND
2-WIRE INTERFACE
LINE FEED CONTROL
4-WIRE INTERFACE VF SIGNAL PATH VBH VBL VCC BATTERY SELECTION AND BIAS NETWORK
PULSE METERING SIGNAL PATH SPM
Related Literature
* AN9871, User's Guide for UniSLIC14 Eval Board * AN9903, UniSLIC14 and TI TCM38C17
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001, 2002, 2004-2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
1
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Ordering Information
PART NUMBER* LINE MAX VOLTAGE LOOP 2 TEST CURRENT POLARITY GND GND MEASUREMENT PULSE RELAY (mA) REVERSAL START KEY METERING DRIVERS 2 WIRE LOOPBACK LONGITUDINAL BALANCE TEMP RANGE (C) PKG. DWG. #
HC55120CB HC55120CBZ Pb-free (Note) HC55120CM HC55120CMZ Pb-free (Note) HC55121IB HC55121IBZ Pb-free (Note) HC55121IM HC55121IMZ Pb-free (Note) HC55130IB HC55130IB96 (Tape and Reel) HC55130IBZ Pb-free (Note) HC55130IBZ96 (Tape and Reel) Pb-free (Note) HC55130IM HC55130IMZ Pb-free (Note) HC55140IB HC55140IBZ Pb-free (Note) HC55140IM HC55140IMZ Pb-free (Note) HC55142IB HC55142IBZ Pb-free (Note) HC55142IM HC55142IM96 (Tape and Reel) HC55142IMZ Pb-free (Note) HC55142IMZ96 (Tape and Reel) Pb-free (Note)
30 30 30 30 30 30 30 30 45 45 45 45
* * * * * * * * * * * * * * * * * * * *
53dB 53dB 53dB 53dB 53dB 53dB 53dB 53dB 63dB 63dB 63dB 63dB
0 to 70 0 to 70 0 to 70 0 to 70
M28.3 SOIC M28.3 SOIC N28.45 PLCC N28.45 PLCC
-40 to 85 M28.3 SOIC -40 to 85 M28.3 SOIC -40 to 85 N28.45 PLCC -40 to 85 N28.45 PLCC -40 to 85 M28.3 SOIC -40 to 85 M28.3 SOIC -40 to 85 M28.3 SOIC -40 to 85 M28.3 SOIC -40 to 85 N28.45 PLCC -40 to 85 N28.45 PLCC -40 to 85 M28.3 SOIC -40 to 85 M28.3 SOIC -40 to 85 N28.45 PLCC -40 to 85 N28.45 PLCC -40 to 85 M28.3 SOIC -40 to 85 M28.3 SOIC -40 to 85 N28.45 PLCC -40 to 85 N28.45 PLCC -40 to 85 N28.45 PLCC -40 to 85 N28.45 PLCC
45 45 45 45 45 45 45 45 45 45 45 45
63dB 63dB
* * * * * * * * * *
* * * * * * * * * *
* * * * * * * * * *
* * * * * * * * * * * * * * * *
* * * * * * * * * *
63dB 63dB 63dB 63dB 63dB 63dB 63dB 63dB 63dB 63dB
2
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Ordering Information (Continued)
PART NUMBER* LINE MAX VOLTAGE LOOP 2 TEST CURRENT POLARITY GND GND MEASUREMENT PULSE RELAY (mA) REVERSAL START KEY METERING DRIVERS 2 WIRE LOOPBACK LONGITUDINAL BALANCE TEMP RANGE (C) PKG. DWG. #
* * * * * *
HC55143IM HC55143IMZ Pb-free (Note) HC55150CB HC55150CBZ Pb-free (Note) HC55150CM HC55150CMZ Pb-free (Note) HC5514XEVAL1
45 45 45 45 45 45
* * * * * *
* *
* *
* * * * * *
* * * * * *
* *
63dB 63dB 55dB 55dB 55dB 55dB
-40 to 85 N32.45x55 PLCC -40 to 85 N32.45x55 PLCC 0 to 70 0 to 70 0 to 70 0 to 70 M28.3 SOIC M28.3 SOIC N28.45 PLCC N28.45 PLCC
Evaluation board
Available by placing SLIC in Test mode.
*Part marking is the same as the part number on all parts. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Device Operating Modes
C3 0 C2 0 C1 0 DESCRIPTION Open Circuit 4-Wire Loopback Ringing Forward Active Test Forward Active 2 Wire Loopback and Line Voltage Measurement Tip Open Ground Start Reserved Reverse Active Test Reverse Active Line Voltage Measurement HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
* * *
* * * *
* * *
* * * *
* * * *
* * * *
0 0 0
0 1 1
1 0 1
1 1 1 1
0 0 1 1
0 1 0 1
* * * * * * * *
* * * * * * *
3
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
Absolute Maximum Ratings TA = 25C
Temperature, Humidity Storage Temperature Range . . . . . . . . . . . . . . . . .-65C to 150C Operating Temperature Range. . . . . . . . . . . . . . . . -40C to 110C Operating Junction Temperature Range . . . . . . . .-40C to 150C Power Supply (-40C TA 85C) Supply Voltage VCC to GND . . . . . . . . . . . . . . . . . . . . -0.4V to 7V Supply Voltage VBL to GND . . . . . . . . . . . . . . . . . . . .-VBH to 0.4V Supply Voltage VBH to GND, Continuous . . . . . . . . . -75V to 0.4V Supply Voltage VBH to GND, 10ms . . . . . . . . . . . . . . -80V to 0.4V Relay Driver Ring Relay Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 0V to 14V Ring Relay Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Digital Inputs, Outputs (C1, C2, C3, C4, C5, SHD, GKD_LVM) Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to VCC Output Voltage (SHD, GKD_LVM Not Active) . . . . . -0.4V to VCC Output Current (SHD, GKD_LVM) . . . . . . . . . . . . . . . . . . . . . 5mA ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V Gate Count. . . . . . . . . . . . . . . . . . . . . . . 543 Transistors, 51 Diodes Tipx and Ringx Terminals (-40C TA 85C) Tipx or Ringx Current . . . . . . . . . . . . . . . . . . . . -100mA to 100mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA 28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . 52C/W 28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . 45C/W 32 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . 66.2C/W Continuous Power Dissipation at 85C 28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W 28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0W 32 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4W Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . 300C (PLCC, SOIC - Lead Tips Only) Derate above 70C
Tip and Ring Terminals
Tipx or Ringx, Current, Pulse < 10ms, TREP > 10s . . . . . . . . . .2A Tipx or Ringx, Current, Pulse < 1ms, TREP > 10s . . . . . . . . . . .5A Tipx or Ringx, Current, Pulse < 10s, TREP > 10s . . . . . . . . .15A Tipx or Ringx, Current, Pulse < 1s, TREP > 10s . . . . . . . . . .20A Tipx or Ringx, Pulse < 250ns, TREP > 10s 20A
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Typical Operating Conditions
These represent the conditions under which the device was developed and are suggested as guidelines. PARAMETER Ambient Temperature CONDITIONS HC55120, HC55150/1 HC55121, HC55130/1, HC55140/1, HC55142/3 VBH with Respect to GND VBL with Respect to GND VCC with Respect to GND MIN 0 -40 TYP MAX 70 85 UNITS C C
-58 VBH 4.75
-
-8 0 5.25
V V V
4
FN4659.13 June 1, 2006
Electrical Specifications
TA = -40C to 85C, VCC = +5V 5%, VBH = -48V, VBL = -24V, PTG = Open, RP1 = RP2 = 0, ZT = 120k, RLIM = 38.3k, RD = 50k, RDC_RAC = 20k, ROH = 40k, CH = 0.1F, CDC = 4.7F, CRT/REV = 0.47F, GND = 0V, RL = 600. Unless Otherwise Specified. (*) Symbol used to indicate the test applies to the part. (NA) symbol used to indicate the test does not apply to the part.
TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
PARAMETER
2-WIRE PORT Overload Level, Off Hook Forward and Reverse Overload Level, On Hook Forward and Reverse Input Impedance (Into Tip and Ring) 1% THD, IDCMET 18mA (Note 2, Figure 1) 1% THD, IDCMET 5mA (Note 3, Figure 1) 3.2 1.3 ZT /200 0 VPEAK VPEAK /Wire Forward Only Forward Only
* * * * *
AT 300
Forward Only Forward Only
* * * * *
VTX
* * * * *
* * * * *
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
*
Forward Only Forward Only
*
Forward Only Forward Only
5
FN4659.13 June 1, 2006
Longitudinal Impedance (Tip, Ring) 0 < f < 100Hz (Note 4, Figure 2) Forward and Reverse LONGITUDINAL CURRENT LIMIT (TIP, RING) On-Hook, Off-Hook (Active), RL = 736 Forward and Reverse No False Detections, (Loop Current), LB > 45dB (Notes 5, 6, Figures 3A, 3B)
28
-
-
mARMS/Wire
TIP VTR RL IDCMET
VTX
1VRMS 0 < f < 100Hz EL C
TIP VT
300 ERX RING VRX AR
VR RING VRX
LZT = VT/AT
LZR = VR/AR
FIGURE 1. OVERLOAD LEVEL (OFF HOOK, ON HOOK)
FIGURE 2. LONGITUDINAL IMPEDANCE
368 A 10F EL 10F C A 368 RING SHD VRX C EL TIP VTX C
368 A TIP VTX VTX
A 368
RING SHD
VRX
FIGURE 3A. LONGITUDINAL CURRENT LIMIT ON-HOOK (ACTIVE)
FIGURE 3B. LONGITUDINAL CURRENT LIMIT OFF-HOOK (ACTIVE)
Electrical Specifications
TA = -40C to 85C, VCC = +5V 5%, VBH = -48V, VBL = -24V, PTG = Open, RP1 = RP2 = 0, ZT = 120k, RLIM = 38.3k, RD = 50k, RDC_RAC = 20k, ROH = 40k, CH = 0.1F, CDC = 4.7F, CRT/REV = 0.47F, GND = 0V, RL = 600. Unless Otherwise Specified. (*) Symbol used to indicate the test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
PARAMETER
OFF-HOOK LONGITUDINAL BALANCE MIN Longitudinal to Metallic (Note 7) Forward and Reverse IEEE 455 - 1985, RLR, RLT = 368 Normal Polarity: 0.2kHz < f < 1.0kHz, 0C to 70C 1.0kHz < f < 3.4kHz, 0C to 70C dB dB dB dB dB Forward Only 53 53 NA NA NA MIN Longitudinal to Metallic (Note 7) Forward and Reverse RLR, RLT = 300, Normal Polarity: 0.2kHz < f < 1.0kHz, 0C to 70C 1.0kHz < f < 3.4kHz, 0C to 70C 0.2kHz < f < 1.0kHz, -40C to 85C 1.0kHz < f < 3.4kHz, -40C to 85C Reverse Polarity 0.2kHz < f < 3.4kHz, (Figure 4) Longitudinal to 4-Wire (Note 9) (Forward and Reverse) Normal Polarity: 0.2kHz < f < 1.0kHz, 0C to 70C 1.0kHz < f < 3.4kHz, 0C to 70C 0.2kHz < f < 1.0kHz, -40C to 85C 1.0kHz < f < 3.4kHz, -40C to 85C Reverse Polarity 0.2kHz < f < 3.4kHz, (Figure 4) Metallic to Longitudinal (Note 10) Forward and Reverse 4-Wire to Longitudinal (Note 11) Forward and Reverse FCC Part 68, Para 68.310 (Note 8) 0.2kHz < f < 3.4kHz, (Figure 5) 0.2kHz < f < 3.4kHz, (Figure 5) 40 40 50 dB dB dB dB dB dB dB dB dB dB dB dB Forward Only 53 53 NA NA NA MIN Forward Only 53 53 NA NA NA Forward Only Forward Only NA NA 53 53 53 NA NA 53 53 53 MIN NA NA 53 53 53 MIN MIN MIN Forward Only NA NA 63 58 NA MIN Forward Only NA NA 63 58 NA MIN Forward Only NA NA 63 58 NA Forward Only Forward Only NA NA 63 58 58 NA NA 63 58 58 61 61 NA NA 61 NA NA 63 58 58 MIN NA NA 63 58 58 MIN 55 55 NA NA 55 MIN NA NA 63 58 58 MIN NA NA 63 58 58 MIN 55 55 NA NA 55 MIN MIN MIN MIN
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
6
FN4659.13 June 1, 2006
0.2kHz < f < 1.0kHz, -40C to 85C 1.0kHz < f < 3.4kHz, -40C to 85C Reverse Polarity 0.2kHz < f < 3.4kHz, (Figure 4)
* *
* *
* *
* *
Electrical Specifications
TA = -40C to 85C, VCC = +5V 5%, VBH = -48V, VBL = -24V, PTG = Open, RP1 = RP2 = 0, ZT = 120k, RLIM = 38.3k, RD = 50k, RDC_RAC = 20k, ROH = 40k, CH = 0.1F, CDC = 4.7F, CRT/REV = 0.47F, GND = 0V, RL = 600. Unless Otherwise Specified. (*) Symbol used to indicate the test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
TEST CONDITIONS RLT TIP VTX VTX VTR 2.16F C VL RING RLR VRX RLR RING 300 VRX MIN TYP MAX UNITS HC55120 RLT TIP 300 ETR ERX VTX HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
PARAMETER
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
EL
C 2.16F
7
2-Wire Return Loss Forward and Reverse TIP IDLE VOLTAGE (User Programmable) TIPX Idle Voltage Forward and Reverse RING IDLE VOLTAGE (User Programmable) RINGX Idle Voltage Forward and Reverse VTR Forward and Reverse VTR(ROH) Pulse Metering Forward and Reverse
ZD R VS R ZIN VM RLR
FN4659.13 June 1, 2006
FIGURE 4. LONGITUDINAL TO METALLIC AND LONGITUDINAL TO 4-WIRE BALANCE 0.2kHz to 1.0kHz (Note 12, Figure 6) 1.0kHz to 3kHz (Note 12, Figure 6) 3kHz to 3.4kHz (Note 12, Figure 6) Active, IL < 5mA 30 23 21 -2.6 35 25 23 -2.2
FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO LONGITUDINAL BALANCE -1.8 dB dB dB V Forward Only Forward Only Forward Only
*
Forward Only
*
*
*
* * * *
* * *
NA
* * * *
* * * *
Active, IL < 5mA Tip open, IL < 5mA Active, IL < 5mA Active, IL 8.5mA, ROH = 50k
-46.4 -46.4 41 36
-45.3 -45.3 43.1 38.1
-44.2 -44.2 45 -
V V V V
Forward Only Forward Only NA
Forward Only Forward Only NA
TIP
VTX VTR 600 EG RL
TIP
VTX VTX ZL
RING
VRX
RING
VRX
FIGURE 6. TWO-WIRE RETURN LOSS
FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT), OUTPUT OFFSET VOLTAGE AND HARMONIC DISTORTION
Electrical Specifications
TA = -40C to 85C, VCC = +5V 5%, VBH = -48V, VBL = -24V, PTG = Open, RP1 = RP2 = 0, ZT = 120k, RLIM = 38.3k, RD = 50k, RDC_RAC = 20k, ROH = 40k, CH = 0.1F, CDC = 4.7F, CRT/REV = 0.47F, GND = 0V, RL = 600. Unless Otherwise Specified. (*) Symbol used to indicate the test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
PARAMETER
4-WIRE TRANSMIT PORT (VTX) Overload Level, Off Hook (IL 18mA) (ZL > 20k, IL 1% THD) (Note 13, Forward and Reverse Figure 7) TA = 0C to 85C TA = -40C to 0C Overload Level, On Hook (IL 5mA) (ZL > 20k, 1% THD) Forward and Reverse (Note 14, Figure 7) VTX Output Offset Voltage Forward and Reverse Output Impedance (Guaranteed by Design) 4-WIRE RECEIVE PORT (VRX) VRX Input Impedance (Guaranteed by Design) 2-Wire to 4-Wire Forward and Reverse 0.2kHz < f < 3.4kHz 500 600 k EG = 0, ZL = , (Note 15, Figure 7) 0.2kHz < f < 03.4kHz 3.2 3.0 1.3 -200 0.1 200 1 VPEAK VPEAK VPEAK mV Forward Only Forward Only Forward Only
* * * * *
Forward Only
* * * * *
* * * * *
* * * * *
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
Forward Only Forward Only
8
FN4659.13 June 1, 2006
* *
Forward Only
* *
Forward Only
FREQUENCY RESPONSE (OFF-HOOK) Relative to 0dBm at 1.0kHz, ERX = 0V 0.3kHz < f < 3.4kHz f = 8.0kHz (Note 16, Figure 8) f = 12kHz (Note 16, Figure 8) f = 16kHz (Note 16, Figure 8) 4-Wire to 2-Wire Forward and Reverse Relative to 0dBm at 1.0kHz, EG = 0V 0.3kHz < f < 3.4kHz f = 8kHz (Note 17, Figure 8) f = 12kHz (Note 17, Figure 8) f = 16kHz (Note 17, Figure 8) 4-Wire to 4-Wire Forward and Reverse Relative to 0dBm at 1.0kHz, EG = 0V 0.3kHz < f < 3.4kHz (Note 18, Figure 8) -0.15 8kHz, 12kHz, 16kHz (Note 18, Figure 8)
TIP RL 600 VTX VTX EG OPEN VTR PTG ERX RING VRX RING VRX RL 600 VTR
-0.15 -0.15 -0.5 -1.0 -1.5
0.24 0.58 1.0 0.24 0.58 1.0 0
0.15 0.5 1.0 1.5 0.15 0.15 0.5
dB dB dB dB dB dB dB dB dB dB
*
Forward Only Forward Only
*
*
*
*
Forward Only Forward Only
*
*
*
*
TIP
*
*
*
-0.5
VTX VTX
FIGURE 8. FREQUENCY RESPONSE, INSERTION LOSS, GAIN TRACKING AND HARMONIC DISTORTION
FIGURE 9. IDLE CHANNEL NOISE
Electrical Specifications
TA = -40C to 85C, VCC = +5V 5%, VBH = -48V, VBL = -24V, PTG = Open, RP1 = RP2 = 0, ZT = 120k, RLIM = 38.3k, RD = 50k, RDC_RAC = 20k, ROH = 40k, CH = 0.1F, CDC = 4.7F, CRT/REV = 0.47F, GND = 0V, RL = 600. Unless Otherwise Specified. (*) Symbol used to indicate the test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
PARAMETER
INSERTION LOSS 2-Wire to 4-Wire Forward and Reverse 0dBm, 1kHz PTG = Open (Note 19, Figure 8) PTG = GND (Note 20, Figure 8) 4-Wire to 2-Wire Forward and Reverse 0dBm, 1kHz (Note 21, Figure 8) -0.2 -6.22 -0.2 -6.02 0.2 -5.82 0.2 dB dB dB Forward Only Forward Only Forward Only Forward Only
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
* * * *
Forward Only Forward Only Forward Only Forward Only
* * * *
* * * *
* * * *
9
FN4659.13 June 1, 2006
GAIN TRACKING (Ref = -10dBm, at 1.0kHz) 2-Wire to 4-Wire Forward and Reverse 4-Wire to 2-Wire Forward and Reverse NOISE Idle Channel Noise at 2-Wire Forward and Reverse Idle Channel Noise at 4-Wire Forward and Reverse HARMONIC DISTORTION 2-Wire to 4-Wire Forward and Reverse 4-Wire to 2-Wire Forward and Reverse 0dBm, 0.3kHz to 3.4kHz (Note 26, Figure 7) 0dBm, 0.3kHz to 3.4kHz (Note 27, Figure 8)
TIP VTX RLIM VTR RLIM 38.3k IR1 R1 RING VRX RING VRX
-40dBm to +3dBm (Note 22, Figure 8) -55dBm to -40dBm (Note 22, Figure 8) -40dBm to +3dBm (Note 23, Figure 8) -55dBm to -40dBm (Note 23, Figure 8) C-Message Weighting Psophometric Weighting (Note 24, Note 30, Figure 9) C-Message Weighting Psophometrical Weighting (Note 25, Note 30, Figure 9)
-0.1 -0.2 -0.1 -0.2 -
10.5 -79.5 10.5 -79.5
0.1 0.2 0.1 0.2 13 -77 13 -77
dB dB dB dB dBrnC dBmp dBrnC dBmp
Forward Only Forward Only
* * * *
7k S
Forward Only Forward Only
* * * *
VTX
* * * *
* * * *
-
-67 -67
-50 -50
dB dB
Forward Only Forward Only
VBH
Forward Only Forward Only
TIP
RL 600
FIGURE 10. CONSTANT LOOP CURRENT TOLERANCE
FIGURE 11. TIPX VOLTAGE
Electrical Specifications
TA = -40C to 85C, VCC = +5V 5%, VBH = -48V, VBL = -24V, PTG = Open, RP1 = RP2 = 0, ZT = 120k, RLIM = 38.3k, RD = 50k, RDC_RAC = 20k, ROH = 40k, CH = 0.1F, CDC = 4.7F, CRT/REV = 0.47F, GND = 0V, RL = 600. Unless Otherwise Specified. (*) Symbol used to indicate the test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
PARAMETER
BATTERY FEED CHARACTERISTICS Constant Loop Current Tolerance IL = 26.5mA, RLIM = 38.3k Forward and Reverse Tip Open State TIPX Leakage Current 18mA IL 45mA, (Note 27, Figure 10) S = Closed (Figure 11) R1 = 0, VBH = -48V, RLIM = 38.3k R1 = 2.5k, VBH = -48V (Figure 11) Tip Open State RINGX Voltage Tip Voltage (Ground Start) Tip Voltage (Ground Start) 5mA < IR1 < 26mA (Figure 11) Active State, (S Open) R1 = 150 (Figure 11) Active State, (S Closed) Tip Lead to -48V Through 7k, Ring Lead to Ground Through 150 (Figure 11) Open Circuit State Loop Current LOOP CURRENT DETECTOR Programmable Threshold Forward and Reverse GROUND KEY DETECTOR Ground Key Detector Threshold Tip/Ring Current Difference LINE VOLTAGE MEASUREMENT Pulse Width (GKD_LVM) RING TRIP DETECTOR (DT, DR) Ring Trip Comparator Current Input Common-Mode Range Source Res = 2M Source Res = 2M 2 200 A V Pulse Width = (20)(CREV.../ILIM) 0.32 0.36 0.4 ms/V NA NA NA Tip Open Active (Note 29, R1 = 2.5k, Figure 12) 5 12.5 8 20 11 27.5 mA mA ILTh = (500/ RD) 5mA, ILTh = 8.5mA RD = 58.8k NA NA 0.9ILTh ILTh 1.1ILTh mA Forward Only (Active) RL = 0 -5.3 -20 -4.8 0 -4.3 20 V A NA NA NA 0.92IL 22.6 15.5 -5.3 IL 26.8 17.1 42.8 -4.8 1.08IL -200 31 18.2 -4.3 mA A mA mA V V Forward Only
* * * *
NA
Forward Only
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
* * * * * * * *
* * * * * * * *
* * * *
NA
* * *
NA
* * *
NA
10
FN4659.13 June 1, 2006
Tip Open State RINGX Current
NA
*
* *
*
Forward Only
* *
*
*
* * * *
* * * *
* * *
* *
* *
* *
Electrical Specifications
TA = -40C to 85C, VCC = +5V 5%, VBH = -48V, VBL = -24V, PTG = Open, RP1 = RP2 = 0, ZT = 120k, RLIM = 38.3k, RD = 50k, RDC_RAC = 20k, ROH = 40k, CH = 0.1F, CDC = 4.7F, CRT/REV = 0.47F, GND = 0V, RL = 600. Unless Otherwise Specified. (*) Symbol used to indicate the test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
PARAMETER
RING RELAY DRIVER VSAT at 30mA VSAT at 40mA Off State Leakage Current IOL = 30mA IOL = 40mA VOH = 13.2V 0.2 0.52 0.1 0.5 0.8 10 V V A
* * *
NA NA NA
* * *
NA NA NA
* * *
NA/* NA/* NA/*
* * *
NA/* NA/* NA/*
* * *
NA/* NA/* NA/*
* * *
NA/* NA/* NA/*
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
TEST RELAY DRIVER (TRLY1, TRLY2) VSAT at 30mA VSAT at 40mA Off State Leakage Current IOL = 30mA IOL = 40mA VOH = 13.2V 0.3 0.65 TIP
11
FN4659.13 June 1, 2006
0.5 1.3 10
V V A
VTX
RING 2.5k
VRX SHD
FIGURE 12. GROUND KEY DETECT DIGITAL INPUTS (C1, C2, C3, C4, C5) Input Low Voltage, VIL Input High Voltage, VIH Input Low Current, IIL Input High Current, IIH VIL = 0.4V VIH = 2.5V 0 2.0 25 0.8 VCC -10 50 V V A A
* * * *
Forward Only Forward Only GKD GKD
* * * * * *
GKD GKD
* * * *
Forward Only Forward Only NA NA
* * * * * *
GKD_ LVM GKD_ LVM
* * * * * *
GKD_ LVM GKD_ LVM
* * * * * *
LVM LVM
DETECTOR OUTPUTS (SHD, GKD_LVM) SHD Output Low Voltage, VOL Forward, Reverse SHD Output High Voltage, VOH Forward, Reverse GKD_LVM Output Low Voltage, VOL Forward and Tip Open GKD_LVM Output High Voltage, VOH Forward and Tip Open Internal Pull-Up Resistor IOL = 1mA IOH = 100A IOL = 1mA R1 = 2.5k (Figure 11) IOH = 100A 2.7 2.7 15 0.5 0.5 V V V V k
*
*
*
*
*
*
Electrical Specifications
TA = -40C to 85C, VCC = +5V 5%, VBH = -48V, VBL = -24V, PTG = Open, RP1 = RP2 = 0, ZT = 120k, RLIM = 38.3k, RD = 50k, RDC_RAC = 20k, ROH = 40k, CH = 0.1F, CDC = 4.7F, CRT/REV = 0.47F, GND = 0V, RL = 600. Unless Otherwise Specified. (*) Symbol used to indicate the test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
PARAMETER
POWER DISSIPATION (VBH = -48V, VBL = -24V) Open Circuit State On-Hook, Active Forward and Reverse C1, C2, C3 = 0, 0, 0 C1, C2, C3 = 0, 1, 0 C1, C2, C3 = 1, 1, 0 IL = 0mA, Longitudinal Current = 0mA Open Circuit State 52 mW Forward Only Forward Only Forward Only Forward Only Forward Only Forward Only Forward Only Forward Only Forward Only Forward Only * 25 mW Forward Only
* * * * * * * * * * * * *
Forward Only
* *
* * * * * * * * * * * * *
* * * * * * * * * * * * *
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
Forward Only Forward Only Forward Only Forward Only Forward Only Forward Only Forward Only Forward Only Forward Only Forward Only
* * * * * * * * * * *
12
VCC Current, ICC VBH Current, IBH VBL Current, IBL VCC Current, ICC Forward and Reverse VBH Current, IBH Forward and Reverse VBL Current, IBL Forward and Reverse VCC to 2 or 4 Wire Port Forward and Reverse VBH to 2 or 4 Wire Port Forward and Reverse VBL to 2 or 4 Wire Port Forward and Reverse TEMPERATURE GUARD Junction Threshold Temperature
FN4659.13 June 1, 2006
POWER SUPPLY CURRENTS (VBH = -48V, VBL = -24V) Active State IL = 0mA, Longitudinal Current = 0mA 2.25 0.3 0.022 2.7 0.8 3.0 0.45 0.035 3.6 1.06 0.01 mA mA mA mA mA mA
POWER SUPPLY REJECTION RATIOS Active State RL = 600 50Hz < f < 3400Hz, VIN =100mV 40 40 40 dB dB dB
-
175
-
C
*
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Notes
2. Overload Level (Two-Wire Port, Off Hook) - The overload level is specified at the 2-wire port (VTR) with the signal source at the 4-wire receive port (ERX). RL = 600, IDCMET 18mA. Increase the amplitude of ERX until 1% THD is measured at VTR. Reference Figure 1. 3. Overload Level (Two-Wire Port, On Hook) - The overload level is specified at the 2-wire port (VTR) with the signal source at the 4-wire receive port (ERX). RL = , IDCMET = 0mA. Increase the amplitude of ERX until 1% THD is measured at VTR. Reference Figure 1. 4. Longitudinal Impedance - The longitudinal impedance is computed using the following equations, where TIP and RING voltages are referenced to ground. LZT, LZR, VT, VR, AR and A T are defined in Figure 2. (TIP) LZT = VT /AT (RING) LZR = VR /AR where: EL = 1VRMS (0Hz to 100Hz) 5. Longitudinal Current Limit (On-Hook Active) - On-Hook longitudinal current limit is determined by increasing the (60Hz) amplitude of EL (Figure 3A) until the 2-wire longitudinal current is greater than 28mARMS/Wire. Under this condition, SHD pin remains low (no false detection) and the 2-wire to 4-wire longitudinal balance is verified to be greater than 45dB (LB2-4 = 20log VTX/EL). 6. Longitudinal Current Limit (Off-Hook Active) - Off-Hook longitudinal current limit is determined by increasing the (60Hz) amplitude of EL (Figure 3B) until the 2-wire longitudinal current is greater than 28mARMS/Wire. Under this condition, SHD pin remains high (no false detection) and the 2-wire to 4-wire longitudinal balance is verified to be greater than 45dB (LB2-4 = 20log VTX/EL). 7. Longitudinal to Metallic Balance - The longitudinal to metallic balance is computed using the following equation: BLME = 20 log (EL /VTR), where: EL and VTR are defined in Figure 4. 8. Metallic to Longitudinal FCC Part 68, Para 68.310 - The metallic to longitudinal balance is defined in this spec. 9. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire balance is computed using the following equation: BLFE = 20 log (EL /VTX), EL and VTX are defined in Figure 4. 10. Metallic to Longitudinal Balance - The metallic to longitudinal balance is computed using the following equation: BMLE = 20 log (ETR /VL), ERX = 0 where: ETR, VL and ERX are defined in Figure 5. 11. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal balance is computed using the following equation: BFLE = 20 log (ERX /VL), ETR = source is removed. where: ERX, VL and ETR are defined in Figure 5. 12. Two-Wire Return Loss - The 2-wire return loss is computed using the following equation: r = -20 log (2VM /VS) where: ZD = The desired impedance; e.g., the characteristic impedance of the line, nominally 600. (Reference Figure 6). 13. Overload Level (4-Wire Port Off-Hook) - The overload level is specified at the 4-wire transmit port (VTX) with the signal source (EG) at the 2-wire port, ZL = 20k, RL = 600 (Reference Figure 7). Increase the amplitude of EG until 1% THD is measured at VTX. Note the PTG pin is open, and the gain from the 2-wire port to the 4-wire port is equal to 1. 14. Overload Level (4-Wire Port On-Hook) - The overload level is specified at the 4-wire transmit port (VTX) with the signal source (EG) at the 2-wire port, ZL = 20k, RL = (Reference Figure 7). Increase the amplitude of EG until 1% THD is measured at VTX. Note the PTG pin is open, and the gain from the 2-wire port to the 4-wire port is equal to 1. 15. Output Offset Voltage - The output offset voltage is specified with the following conditions: EG = 0, RL = 600, ZL = and is measured at VTX. EG, RL, VTX and ZL are defined in Figure 7. 16. Two-Wire to Four-Wire Frequency Response - The 2-wire to 4-wire frequency response is measured with respect to EG = 0dBm at 1.0kHz, ERX = 0V (VRX input floating), RL = 600. The frequency response is computed using the following equation: F2-4 = 20 log (VTX /VTR), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTX, VTR, RL and EG are defined in Figure 8. 17. Four-Wire to Two-Wire Frequency Response - The 4-wire to 2wire frequency response is measured with respect to ERX = 0dBm at 1.0kHz, EG source removed from circuit, RL = 600. The frequency response is computed using the following equation: F4-2 = 20 log (VTR /ERX), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTR, RL and ERX are defined in Figure 8. 18. Four-Wire to Four-Wire Frequency Response - The 4-wire to 4-wire frequency response is measured with respect to ERX = 0dBm at 1.0kHz, EG source removed from circuit, RL = 600. The frequency response is computed using the following equation: F4-4 = 20 log (VTX /ERX), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTX , RL and ERX are defined in Figure 8. 19. Two-Wire to Four-Wire Insertion Loss (PTG = Open) - The 2-wire to 4-wire insertion loss is measured with respect to EG = 0dBm at 1.0kHz input signal, ERX = 0 (VRX input floating), RL = 600 and is computed using the following equation: L2-4 = 20 log (VTX /VTR) where: VTX, VTR, RL and EG are defined in Figure 8. (Note: The fuse resistors, RF , impact the insertion loss. The specified insertion loss is for RF1 = RF2 = 0). 20. Two-Wire to Four-Wire Insertion Loss (PTG = AGND) - The 2-wire to 4-wire insertion loss is measured with respect to EG = 0dBm at 1.0kHz input signal, ERX = 0 (VRX input floating), RL = 600 and is computed using the following equation: L2-4 = 20 log (VTX /VTR) where: VTX, VTR, RL and EG are defined in Figure 8. (Note: The fuse resistors, RF , impact the insertion loss. The specified insertion loss is for RF1 = RF2 = 0). 21. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire insertion loss is measured based upon ERX = 0dBm, 1.0kHz input signal, EG source removed from circuit, RL = 600 and is computed using the following equation: L4-2 = 20 log (VTR /ERX) where: VTR, RL and ERX are defined in Figure 8. 22. Two-Wire to Four-Wire Gain Tracking - The 2-wire to 4-wire gain tracking is referenced to measurements taken for EG = -10dBm, 1.0kHz signal, ERX = 0 (VRX output floating), RL = 600 and is computed using the following equation. G2-4 = 20 * log (VTX /VTR) vary amplitude -40dBm to +3dBm, or -55dBm to -40dBm and compare to -10dBm reading. VTX, RL and VTR are defined in Figure 8.
13
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
23. Four-Wire to Two-Wire Gain Tracking - The 4-wire to 2-wire gain tracking is referenced to measurements taken for ERX = -10dBm, 1.0kHz signal, EG source removed from circuit, RL = 600 and is computed using the following equation: G4-2 = 20 * log (VTR /ERX) vary amplitude -40dBm to +3dBm, or -55dBm to -40dBm and compare to -10dBm reading. VTR, RL and ERX are defined in Figure 8. The level is specified at the 4-wire receive port and referenced to a 600 impedance level. 24. Two-Wire Idle Channel Noise - The 2-wire idle channel noise at VTR is specified with the 2-wire port terminated in 600 (RL) and with the 4-wire receive port (VTX) floating (Reference Figure 9). 25. Four-Wire Idle Channel Noise - The 4-wire idle channel noise at VTX is specified with the 2-wire port terminated in 600 (RL). The noise specification is with respect to a 600 impedance level at VTX. The 4-wire receive port (VTX) floating (Reference Figure 9). 26. Harmonic Distortion (2-Wire to 4-Wire) - The harmonic distortion is measured within the voice band with the following conditions. EG = 0dBm at 1kHz, RL = 600. Measurement taken at VTX. (Reference Figure 7). 27. Harmonic Distortion (4-Wire to 2-Wire) - The harmonic distortion is measured within the voice band with the following conditions. ERX = 0dBm0. Vary frequency between 300Hz and 3.4kHz, RL = 600. Measurement taken at VTR. (Reference Figure 8). 28. Constant Loop Current - The constant loop current is calculated using the following equation: IL = 1000/RLIM = VTR/600 (Reference Figure 10). 29. Ground Key Detector - (TRIGGER) Ground the Ring pin through a 2.5k resistor and verify that GKD goes low. (RESET) Disconnect the Ring pin and verify that GKD goes high. (Hysteresis) Compare difference between trigger and reset. 30. Electrical Test - Not tested in production at -40C.
Circuit Operation and Design Information
The UniSLIC14 family of SLICs are voltage feed current sense Subscriber Line Interface Circuits (SLIC). For short loop applications, the voltage between the tip and ring terminals varies to maintain a constant loop current. For long loop applications, the voltage between the tip and ring terminals are relatively constant and the loop current varies in proportion to the load. The tip and ring voltages for various loop resistances are shown in Figure 13. The tip voltage remains relatively constant as the ring voltage moves to limit the loop current for short loops. The loop current for various loop resistances are shown in Figure 14. For short loops, the loop current is limited to the programmed current limit, set by RILIM. For long loop applications, the loop current varies in accordance with Ohms law for the given tip to ring voltage and the loop resistance.
0 TIP AND RING VOLTAGES (V) -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 CONSTANT LOOP CURRENT REGION 200 600 1000 1400 1800 2000 4K 6K 8K RING CONSTANT TIP TO RING VOLTAGE REGION VBH = -48V RD = 41.2k ROH = 38.3k RDC_RAC = 19.6k RILim = 33.2k -44.5V TIP -2.5V
.
35 30 LOOP CURRENT (mA) 25 20 15 10 5 0 VBH = -48V RD = 41.2k ROH = 38.3k RDC_RAC = 19.6k RILim = 33.2k CONSTANT LOOP CURRENT REGION CONSTANT TIP TO RING VOLTAGE REGION
200
600
1K
1.4K 1.8K
2.2K 2.6K 3.0K 3.4K 3.8K
LOOP RESISTANCE ()
FIGURE 14. LOOP CURRENT vs LOOP RESISTANCE
The following discussion separates the SLIC's operation into its DC and AC paths, then follows up with additional circuit and design information.
DC Feed Curve
The DC feed curve for the UniSLIC14 family is user programmable. The user defines the on hook and off hook overhead voltages (including the overhead voltage for off hook pulse metering if applicable), the maximum and minimum loop current limits, the switch hook detect threshold and the battery voltage. From these requirements, the DC feed curve is customized for optimum operation in any given application. An Excel spread sheet to calculate the external components can be downloaded off our web site www.intersil.com/telecom/unislic14.xls.
10K
LOOP RESISTANCE ()
FIGURE 13. TIP AND RING VOLTAGES vs LOOP RESISTANCE
14
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
VBH 2.5V SLIC SELF PROGRAMMING
TIP TO RING ABSOLUTE VOLTAGE (V)
VOH(on) AT LOAD RSAT VOH(off) AT LOAD CONSTANT CURRENT REGION
OO RL
P( m
) ax
60k SLOPE IOH
ISH-
ISHD
ILOOP(min) LOOP CURRENT (mA)
ILOOP(max)
Internal overhead voltage automatically generated by the SLIC.
FIGURE 15. UniSLIC14 DC FEED CURVE
On Hook Overhead Voltage
The on hook overhead voltage at the load (VOH(on) at Load) is independent of the 2.5V VBH battery voltage. Once VOH(on) ON HOOK OVERHEAD set, the on hook voltage remains constant as the VBH battery voltage changes. The ISH- ISHD on hook voltage also remains LOOP CURRENT constant over temperature ISH- = ISHD(0.6) and line leakages up to 0.6 times the Switch Hook Detect threshold (ISHD ). The maximum loop current for a constant on hook overhead voltage is defined as ISH-.
TIP TO RING VOLTAGE DC FEED CURVE VBH
To account for any process and temperature variations in the performance of the SLIC, 1.5V is added to the overhead voltage requirement for the on hook case in Equation 1 and 2.0V for the off hook case in Equation 3. Note the 2.5V overhead is automatically generated in the SLIC and is not part of the external overhead programming.
EXTERNAL PROTECTION RESISTOR 2RP VZL INTERNAL SENSE RESISTORS ZL (LOAD) 2RS REQUIRED OVERHEAD VOLTAGE VOH (ON, OFF) UniSLIC14 TIP AND RING AMPLIFIERS
The on hook overhead voltage, required for a given signal level at the load, must take into account the AC voltage drop across the 2 external protection resistors (RP) and the 2 internal sense resistors (RS) as shown in Figure 16. The AC on hook overload voltage is calculated using Equation 1.
2R P + 2R S V OH ( on ) at Load = V sp ( on ) x 1 + ----------------------------- + 1.5V ZL (EQ. 1
2R P + 2R S V OH ( ON, OFF ) = ----------------------------- V ZL ZL Where: VZL is the required on hook or offhook transmission delivered to the load.
FIGURE 16. OVERHEAD VOLTAGE OF THE TIP AND RING AMPLIFIERS
where VOH(on) at Load = On hook overhead voltage at load Vsp(on) = Required on hook transmission for speech RP = Protection Resistors (Typically 30) RS = Internal Sense Resistors (40) ZL = AC load impedance for (600) 1.5V = Additional on hook overhead voltage requirement 15
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
TIP TO RING VOLTAGE
Off Hook Overhead Voltage
The off hook overhead voltage VOH(off) at Load is VBH also independent of the VBH 2.5V VSAT battery voltage and remains OFF HOOK OVER HEAD constant over temperature. VOH(off) The required off hook overhead voltage is the sum ILOOP(min) of the AC and DC voltage LOOP CURRENT drops across the internal sense resistors (RS), the protection resistors (RP), the required (peak) off hook voltage for speech (Vsp(off)) and the required (peak) off hook voltage for the pulse metering (Vpm(off)), if applicable.
DC FEED CURVE TIP TO RING VOLTAGE
DC FEED CURVE VBH VSAT VOH(off) 2.5V RSAT
When considering the Off hook condition, RSAT is equal to VOH(off) at Load divided by Iloop(min) (Equation 4).
For the given system requirements (recommended application circuit in back of ILOOP(min) data sheet): Iloop (min) = LOOP CURRENT 20mA, Iloop (max) = 30mA, RSAT VOH(off) AT LOAD Vsp(off) = 3.2VPEAK, Vspm(off) = 0VPEAK, ILOOP(min) VOH(off) at Load = 8.34V the value of RSAT(off) is equal to 417 as calculated in Equation 4.
V OH(off) at Load 8.34V R SAT(off) = --------------------------------------- = --------------- = 417 I LOOP(min) 20mA (EQ. 4)
The off hook overhead voltage is defined in Equation 2 and calculated using Equation 3.
V OH ( off ) at Load = V OH ( Rsense ) + V sp ( off ) + V pm ( off ) (EQ. 2)
where: VOH(off) at Load = Off hook overhead voltage at load VOH(Rsense) = Required overhead for the DC voltage drop across sense resistors (2RS x Iloop(max)) Vsp(off) = Required (peak) off hook AC voltage for speech Vpm(off) = Required (peak) off hook AC voltage for pulse metering
2R P + 2R S V OH(off) at Load = 80 x I LOOP ( max ) + V sp ( off ) x 1 + ----------------------------- ZL 2R P + 2R S + V pm ( off ) x 1 + ----------------------------- + 2.0V Z pm (EQ. 3)
Before using this RSAT value, to calculate the RDC_RAC resistor, we need to verify that the on hook requirements will also be met.
TIP TO RING VOLTAGE DC FEED CURVE VBH VSAT VOH(on) RSAT 2.5V
ISH-(min) LOOP CURRENT
VOH(on) AT LOAD ISH-(min)
RSAT
where: 80 = 2Rs + 2RINT (reference Figure 17) Zpm = Pulse metering load impedance (typically 200). 2.0V = Additional off hook overhead voltage requirement
Thus, the on hook overhead requirements of 2.85V will be met if we use the RSAT(off) value.
V OH ( on ) = ( ISH- ) ( R SAT ( off ) ) V OH ( on ) = 7.2mA x 417 V OH ( on ) = 3.0V (EQ. 5)
2.85V R SAT ( on ) = ----------------- = 395 7.2mA
The on hook overhead voltage calculated with the off hook RSAT (RSAT(off)), is given in Equation 5 and equals 3.0V. The on hook overhead calculated with Equation 1 equals 2.85V for the given system requirements (recommended application circuit in back of data sheet): Switch Hook Detect threshold = 12mA, ISH- = (0.6)12mA = 7.2mA, Vsp(on) = 0.775VRMS
RSAT Resistance Calculation
The RSAT resistance of the DC feed curve is used to determine the value of the RDC_RAC resistor (Equation 6). The value of this resistor has an effect on both the on hook and off hook overheads. In most applications the off hook condition will dominate the overhead requirements. Therefore, we'll start by calculating the RSAT value for the off hook conditions and then verify that the on hook conditions are also satisfied.
If the on hook overhead requirement is not met, then we need to use the RSAT(on) value to determine the RDC_RAC resistor value. The external saturation guard resistor RDC_RAC is equal to 50 times RSAT. In the example above RSAT would equal 417 and RDC_RAC would then equal to 20.85k (closest standard value is 21k).
RDC_RAC = 50 x R SAT (EQ. 6)
The Switch Hook Detect threshold current is set by resistor RD and is calculated using Equation 7. For the above
16
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
example RD is calculated to be 41.6k (500/12mA). The next closest standard value is 41.2k.
500 R D = -----------I SHD (EQ. 7)
SHD threshold, 2) minimum loop current requirement or 3) the on and off hook signal levels.
V BH - [ V SAT + 2V + V OH ( off ) ] R LOOP(max) = ------------------------------------------------------------------------------ -2R P I LOOP(min) (EQ. 12)
The true value of ISH-, for the selected value of RD is given by Equation 8:
500 ISH- = --------- (0.6) RD (EQ. 8)
SLIC in the Active Mode
Figure 17 shows a simplified AC transmission model. Circuit analysis yields the following design equations:
1 V A = I M x 2R S x --------- x 200 ( Z TR - 2R P ) x 5 80k IM V A = ------- ( Z TR - 2R P ) 2 Node Equation V RX VA ------------ - ------------ = I X 500k 500k (EQ. 15) (EQ. 13)
For the example above, ISH- equals 7.28mA (500 x 0.6/ 41.2K). Verify that the value of ISH- is above the suspected line leakage of the application. The UniSLIC family will provide a constant on hook voltage level for leakage currents up to this value of line leakage.
TIP TO RING VOLTAGE DC FEED CURVE VBH VSAT VOH(off) IOH 2.5V OFF HOOK OVER HEAD
(EQ. 14)
The ROH resistor, which is used to set the offhook overhead voltage, is calculated using Equations 9 and 10.
Substitute Equation 14 into Equation 15
V RX I M ( Z TR - 2R P ) I X = ------------ - ----------------------------------------500k 1000k Loop Equation I X 500k - V TX + I X 500k = 0 (EQ. 17) (EQ. 16)
IOH is defined as the difference between the ILOOP(min) ISHILOOP(min) and ISH-. LOOP CURRENT Substituting Equation 8 for ISH- into Equation 9 and solving for ROH defines ROH in terms of ILOOP(min) and RD.
500 500 R OH = --------- = ------------------------------------------I LOOP(min) - ISHI OH (EQ. 9)
Substitute Equation 16 into Equation 17
V TX = 2V RX - I M ( Z TR - 2RP ) Loop Equation (EQ. 18)
Equation 10 can be used to determine the actual ISH- value resulting from the RD resistor selected. The value of RD should be the next standard value that is lower than that calculated. This will insure meeting the ILOOP(min) requirement. ROH for the above example equals 39.1k.
R D 500 R OH = ----------------------------------------------------------- 500(.6) RD I
LOOP(min)
V TR -I M 2R P + V TX = 0
(EQ. 19)
Substitute Equation 18 into Equation 19
V TR = I M Z TR - 2V RX (EQ. 20)
(EQ. 10)
Substituting -VTR/ZL into Equation 20 for IM and rearranging to solve for VTR results in Equation 21
Z TR V TR 1 + ---------- = - 2 V RX ZL (EQ. 21)
The current limit is set by a single resistor and is calculated using Equation 11.
1000 R LIM = ----------------------------I LOOP(max)
TIP TO RING VOLTAGE DC FEED CURVE
(EQ. 11)
where: VRX = The input voltage at the VRX pin.
The maximum loop resistance is calculated using Equation 12. The 2.5V VSAT resistance of the VOH(off) protection resistors A X) (2RP) is subtracted out P(M RLOO to obtain the maximum ILOOP(min) loop length to meet the LOOP CURRENT required off hook overhead voltage. If RLOOP(MAX) meets the loop length requirements you are done. If the loop length needs to be longer, then consider adjusting one of the following: 1) the
VBH
VA = An internal node voltage that is a function of the loop current detector and the impedance matching networks. IX = Internal current in the SLIC that is the difference between the input receive current and the feedback current. IM = The AC metallic current. RP = A protection resistor (typical 30). ZT = An external resistor/network for matching the line impedance. VTX= The tip to ring voltage at the output pins of the SLIC.
17
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
VTR = The tip to ring voltage including the voltage across the protection resistors. ZL = The line impedance. ZTR = The input impedance of the SLIC including the protection resistors. From Equation 21 and the relationship ZT = 200(ZTR-2RP).
V TR ZL ZL G 4-2 = ---------- = -2 ------------------------- = - 2 --------------------------------------------V RX Z L + ZTR ZT --------- + 2R ZL + P 200 (EQ. 22)
Notice that the phase of the 4-wire to 2-wire signal is 180out of phase with the input signal.
(AC) 4-Wire to 2-Wire Gain
The 4-wire to 2-wire gain is equal to VTR/VRX.
IX 500K RS
20
TIP IM + VTR + EG + VTX + ZTR ZL + IM
+ A=1 + 500K
RINT
20
RP
+
VTX + VTX PTG
IX UniSLIC14
IX
500K
- IM + RP
IX RS
20
RINT IX
20
+ -
500K
VRX + VRX -
RING
+
500K
1/80K 5
500K
VA = IM(ZTR-2RP) 2
ZT
= 200 (ZTR - 2RP)
FIGURE 17. SIMPLIFIED AC TRANSMISSION CIRCUIT
(AC) 2-Wire to 4-Wire Gain
The 2-wire to 4-wire gain is equal to VTX/EG with VRX = 0
Loop Equation - E G + Z L I M + 2R P I M - V TX = 0 (EQ. 23)
Rearranging Equation 27 in terms of EG, and substituting into Equation 26 results in an equation for 2-wire to 4-wire gain, that's a function of the synthesized input impedance of the SLIC (ZTR) and the protection resistors (RP).
V TX Z TR - 2R P G 2-4 = ---------- = ----------------------------V TR Z TR (EQ. 28)
From Equation 18 with VRX = 0
V TX = - I M ( Z TR - 2RP ) (EQ. 24)
Substituting Equation 24 into Equation 23 and simplifying.
E G = I M ( Z L + Z TR ) (EQ. 25)
Notice that the phase of the 2-wire to 4-wire signal is in phase with the input signal.
(AC) 4-Wire to 4-Wire Gain
The 4-wire to 4-wire gain is equal to VTX/VRX, EG = 0. From Equation 18.
V TX = - V TX = - 2 V RX + I M ( Z TR - 2R P ) (EQ. 29)
By design, VTX = -VTX, therefore
V TX I M ( Z TR - 2R P ) ( Z TR - 2R P ) G 2-4 = ---------- = --------------------------------------- = -------------------------------EG I M ( Z L + Z TR ) ( Z L + Z TR ) (EQ. 26)
A more useful form of the equation is rewritten in terms of VTX /VTR. A voltage divider equation is written to convert from EG to VTR as shown in Equation 27.
Z TR V TR = ----------------------- E G Z TR + Z L (EQ. 27)
Substituting -VTR /ZL into Equation 29 for IM results in Equation 30.
V TR ( Z TR - 2R P ) V TX = - 2 V RX - -------------------------------------------ZL (EQ. 30)
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Substituting Equation 21 for VTR in Equation 30 and simplifying results in Equation 31.
V TX Z L + 2R P G 4 - 4 = ----------- = - 2 ----------------------- V RX Z L + Z TR (EQ. 31)
constant on hook overhead voltage (ISH- = ISHD(0.6)) and the value of RSAT(off) is calculated in Equation 4. On hook Ring Voltage
R SAT ( off ) V RING ( onhook ) = V BH + 1.5V + ( ISH ) -------------------------- 2 (EQ. 36)
(AC) 2-Wire Impedance
The AC 2-wire impedance (ZTR) is the impedance looking into the SLIC, including the fuse resistors. The formula to calculate the proper ZT for matching the 2-wire impedance is shown in Equation 32.
Z T = 200 * ( Z TR - 2R P ) (EQ. 32)
The calculation of the ring voltage with respect to ground in the off hook condition is dependent upon whether the SLIC is in current limit or not. The off hook ring to ground voltage (in current limit) is calculated using Equation 37. ILIM is the programmed loop current limit and RL is the load resistance across tip and ring. The minus 0.2V is a correction factor for the 60k slope in Figure 15. Off hook Ring Voltage in Current Limit
V RING ( CL ) = V TIP ( offhook ) - I LOOP ( MAX ) R L - 0.2V (EQ. 37)
Equation 32 can now be used to match the SLIC's impedance to any known line impedance (ZTR). EXAMPLE: Calculate ZT to make ZTR = 600 in series with 2.16F. RP = 30.
1 Z T = 200 600 + ---------------------------------- - ( 2 ) ( 30 ) -6 j2.16X10 (EQ. 33)
ZT = 108k in series with 0.0108F. Note: Some impedance models, with a series capacitor, will cause the op-amp feedback to behave as an open circuit DC. A resistor with a value of about 10 times the reactance of the ZT capacitor (2.16F/200 = 10.8nF) at the low frequency of interest (200Hz for example) can be placed in parallel with the capacitor in order to solve the problem (736k for a 10.8nF capacitor).
The off hook ring to ground voltage (not in current limit) is calculated using Equation 38. The 1.5V results from the SLIC self programming. ILOOP(min) is the minimum loop current allowed by the design and the value of RSAT(off) is calculated in Equation 4. Off hook Ring Voltage not in Current Limit
R SAT ( off ) V RING ( NCL ) = V BH + 1.5V + ( I LOOP ( min ) ) -------------------------- 2 - I LOOP ( MIN ) x R P (EQ. 38)
Layout Considerations
Systems with Dual Supplies (VBH and VBL)
If the VBL supply is not derived from the VBH supply, it is recommended that an additional diode be placed in series with the VBH supply. The orientation of this diode is anode on pin 8 of the device and cathode to the external supply. This external diode will inhibit large currents and potential damage to the SLIC, in the event the VBH supply is shorted to GND. If VBL is derived from VBH then this diode is not required. Suggested (not required) supply sequence VBH VBL- VCC.
Calculating Tip and Ring Voltages
The on hook tip to ground voltage is calculated using Equation 34. The minus 1.0 volt results from the SLIC self programming. ISH- is the maximum loop current for a constant on hook overhead voltage (ISH- = ISHD(0.6)) and the value of RSAT(off) is calculated in Equation 4. On hook Tip Voltage
R SAToff V TIP ( onhook ) = - 1.0V + - ( ISH- ) --------------------- 2 (EQ. 34)
The off hook tip to ground voltage is calculated using Equation 35. ILOOP(min) is the minimum loop current allowed by the design and the value of RSAT(off) is calculated in Equation 4. Off hook Tip Voltage
R SAT ( off ) V TIP ( offhook ) = - 1V - ( I LOOP ( min ) ) -------------------------2 - I LOOP ( MAX ) x R P (EQ. 35)
Floating the PTG Pin
The PTG pin is a high impedance pin (500k) that is used to program the 2-wire to 4-wire gain to either 0dB or -6dB. If 0dB is required, it is necessary to float the PTG pin. The PC board interconnect should be as short as possible to minimize stray capacitance on this pin. Stray capacitance on this pin forms a low pass filter and will cause the 2-wire to 4-wire gain to roll off at the higher frequencies. If a 2-wire to 4-wire gain of -6dB is required, the PTG pin should be grounded as close to the device as possible.
The on hook ring to ground voltage is calculated using Equation 36. The 1.5 volt results from the SLIC self programming. ISH- is the maximum loop current for a
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SPM Pin
For optimum performance, the PC board interconnect the SPM pin should be as short as possible. If pulses metering is not being used, then this pin should be grounded as close to the device pin as possible.
Layout of the 2-Wire Impedance Matching Resistor ZT
Proper connection to the ZT pin is to have the external ZT network as close to the device pin as possible. The ZT pin is a high impedance pin that is used to set the proper feedback for matching the impedance of the 2-wire side. This will eliminate circuit board capacitance on this pin to maintain the 2-wire return loss across frequency.
RLIM Pin
The current limiting resistor RLIM needs to be as close to the RLIM pin as possible.
TABLE 1. DETECTOR STATES OUTPUT STATE 0 1 C3 0 0 C2 0 0 C1 0 1 SLIC OPERATING STATE Open Circuit State Ringing State (Previous State cannot be Reverse Active State) Forward Active State ACTIVE DETECTOR 4 wire loopback test capability Ring Trip Detector SHD HIGH GKD_ LVM HIGH HIGH
2
0
1
0
Loop Current Detector Ground Key Detector
3
0
1
1
On Hook Loopback Detector Test Active State Requires previous state to be in the Ground Key Detector Forward Active state to determine the On hook or Off hook status of the line. Off Hook Loop Current Detector Line Voltage Detector
LOW HIGH LOW
4 5 6
1 1 1
0 0 1
0 1 0
Tip Open - Ground Start State Reserved Reverse Active State
Ground Key Detector Reserved Loop Current Detector Ground Key Detector N/A N/A
7
1
1
1
On Hook Loop Current Detector Test Reversal Active State Requires previous state to be in the Reverse Active state to determine the Off Hook Loop Current Detector On hook or Off hook status of the line. Line Voltage Detector Thermal Shutdown
HIGH LOW
8
X
X
X
LOW
LOW
Digital Logic Inputs
Table 1 is the logic truth table for the 3V to 5V logic input pins. A combination of the control pins C3, C2 and C1 select 1 of the possible 6 operating states. The 8th state listed is Thermal Shutdown. Thermal Shutdown protection is invoked if a fault condition on the tip or ring causes the junction temperature of the die to exceed 175C. A description of each operating state and the control logic follows:
the PTG pin is grounded, then the amplitude will be approximately the same as its input and 180o out of phase.
Ringing State (C3 = 0, C2 = 0, C1 = 1)
In this state, the output of the ring relay driver pin (RRLY) goes low (energizing the ring relay to connect the ringing signal to the phone) if either of the following two conditions are satisfied: (1) The RSYNC_REV pin is grounded through a resistor This connection enables the RRLY pin to go low the instant the ringing state is invoked, without any regard for the ringing voltage (90VRMS -120VRMS) across the relay contacts. The resistor (34.8k to 70k) is required to limit the current into the RSYNC_REV pin. (2) A ring sync pulse is applied to the RSYNC_REV pin This connection enables the RRLY pin to go low at the command of a ring sync pulse. A ring sync pulse should go
Open Circuit State (C3 = 0, C2 = 0, C1 = 0)
In this state, the tip and ring outputs are in a high impedance condition (>1M). No supervisory functions are available and SHD and GKD outputs are at a TTL high level. 4-wire loopback testing can be performed in this state. With the PTG pin floating, the signal on the VTX output is 180o out of phase and approximately 2 times the VRX input signal. If
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low at zero voltage crossing of the ring signal. This pulse should have a rise and fall time <400s and a minimum pulse width of 2ms. Zero ring current detection is performed automatically inside the SLIC. This feature de-energizes the ring relay slightly before zero current occurs to partially compensate for the delay in the opening of the relay. The SHD output will go low when the subscriber goes off hook. Once SHD is activated, an internal latch will prohibit the re-ringing of the line until the ringing code is removed and then reapplied. The state prior to ringing the phone, can not be the Reverse Active State. In the reverse active state the polarity of the voltage on the CRT_REV_LVM capacitor, will make it appear as if the subscriber is off hook. This subsequently will activate an internal latch prohibiting the ringing of the line. The GKD_LVM output is disabled (TTL high level) during the ringing state. Reference the Section titled "Ringing the Phone" for more information.
Tip Open State (C3 = 1, C2 = 0, C1 = 0)
In this state, the tip output is in a high impedance state (>250k) and the ring output is capable of full operation, i.e. has full longitudinal current capability. The Tip Open/Ground Start state is used to interface to a PBX incoming 2-wire trunk line. When a ground is applied through a resistor to the ring lead, this current is detected and presented as a TTL logic low on the SHD and GKD_LVM output pins.
Reserved (C3 = 1, C2 = 0, C1 = 1)
This state is undefined and reserved for future use.
Reverse Active State (C3 = 1, C2 = 1, C1 = 0)
In this state, the SLIC is fully functional. The ring voltage is more positive than the tip voltage. The tip and ring output voltages are an unbalanced DC feed, reference Figure 13. The polarity reversal time is determined by the RC time constant of the RSYNC_REV resistor and the CRT_REV_LVM capacitor. Capacitor CRT_REV_LVM performs three different functions: Ring trip filtering, polarity reversal time and line voltage measurement. It is recommended that programming of the reversal time be accomplished by changing the value of RSYNC_REV resistor (see Figure 18). The value of RSYNC_REV resistor is limited between 34.8K (10ms) and 73.2k (21ms). Equation 39 gives the formula for programming the reversal time.
RSYNC - REV = 3.47k x ReversalTime ( ms ) (EQ. 39)
Forward Active State (C3 = 0, C2 = 1, C1 = 0)
In this state, the SLIC is fully functional. The tip voltage is more positive than the ring voltage. The tip and ring output voltages are an unbalanced DC feed, reference Figure 13. Both SHD and GKD supervisory functions are active. Reference the section titled "DC Feed Curve" for more information.
Test Active State (C3 = 0, C2 = 1, C1 = 1)
Proper operation of the Test Active State requires the previous state be the Forward Active state to determine the on hook or off hook status of the line. In this state, the SLIC can perform two different tests. If the subscriber is on hook when the state is entered, a loopback test is performed by switching an internal 600 resistor between tip and ring. The current flows through the internal 600 is unidirectional via blocking diodes. (Cannot be used in reverse.) When the loopback current flows, the SHD output will go low and remain there until the state is exited. This is intended to be a short test since the ability to detect subscriber off hook is lost during loopback testing. Reference the section titled "Loopback Tests" for more information. If the subscriber is off hook when the state is entered, a Line Voltage Measurement test is performed. The output of the GKD_LVM pin is a pulse train. The pulse width of the active low portion of the signal is proportional to the voltage across the tip and ring pins. If the loop length is such that the SLIC is operating in constant current, the tip to ring voltage can be used to determine the length of the line under test. The longer the line, the larger the tip to ring voltage and the wider the pulse. This relationship can determine the length of the line for setting gains in the system. Reference the section titled "Operation of Line Voltage Measurement" for more information.
Both SHD and GKD supervisory functions are active. Reference the section titled "Polarity Reversal" for more information.
Test Reversal Active State (C3 = 1, C2 = 1, C1 = 1)
Proper operation of the Test Reversal Active State requires the previous state be the Reverse Active state to determine the on hook or off hook status of the line. If the subscriber is on hook when the state is entered, the SLIC's tip and ring voltages are the same as the Reverse Active state. The SHD output will go low when the subscriber goes off hook and the GKD_LVM output is disabled (TTL level high). (Note: operation is the same as the Reverse Active state with the GKD_LVM output disabled.) If the subscriber is off hook when the state is entered, a Line Voltage Measurement test is performed. The output of the GKD_LVM pin is a pulse train. The pulse width of the active low portion of the signal is proportional to the voltage across the tip and ring pins. If the loop length is such that the SLIC is operating in constant current mode, the tip to ring voltage can be used to determine the length of the line under test. The longer the line, the larger the tip to ring voltage and the wider the pulse. This relationship can determine the length of the line for setting gains in the system. Reference the section titled "Operation of Line Voltage Measurement" for more information.
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Thermal Shutdown
The UniSLIC14's thermal shutdown protection is invoked if a fault condition causes the junction temperature of the die to exceed about 175C. Once the thermal limit is exceeded, both detector outputs go low (SHD and GKD_LVM) and one of two things can happen. For marginal faults where loop current is flowing during the time of the over-temperature condition, foldback loop current limiting reduces the loop current by reducing the tip to ring voltage. An equilibrium condition will exist that maintains the junction temperature at about 175C until the fault condition is removed. For short circuit faults (tip or ring to ground, or to a supply, etc.) that result in an over-temperature condition, the foldback current limiting will try to maintain an equilibrium at about 175C. If the junction temperature keeps rising, the device will thermally shutdown and disconnect tip and ring until the junction temperature falls to approximately 150C. The ring relay driver pin, RRLY, has an internal clamp between it's output and ground. This eliminates the need to place an external snubber diode across the ring relay.
Reducing Impulse Noise During Ringing
With an increase in digital data lines being installed next to analog lines, the threat from impulse noise on analog lines is increasing. Impulse noise can cause large blocks of high speed data to be lost, defeating most error correcting techniques. The UniSLIC14 family has the capability to reduce impulse noise by closing the ring relay at zero voltage and opening the ring relay at zero current. CLOSING THE RING RELAY AT ZERO VOLTAGE Closing the ring relay at zero voltage is accomplished by providing a ring sync pulse to the RSYNC_REV pin. The ring sync pulse is synchronized to go low at the zero voltage crossing of the ring signal. The resistor R1 in Figure 18 limits the current into the RSYNC_REV pin. If a particular polarity reversal time is required, then make R1 equal to the calculated value in Equation 39. If a specific polarity reversal time is not desired, R1 equal to 50k is suggested. The RSYNC_REV pin is designed to allow the ring sync pulse to be present at all times. There is no need to gate the ring sync pulse on and off. The logic control for the RSYNC_REV pin cannot be an open collector. It must be high (push-pull logic output stage / pull up resistor to VCC), low or being clocked by the ring sync pulse. When the RSYNC_REV pin is high the ring relay pin is disabled. When the RSYNC_REV pin is low the ring relay pin is activated the instant the logic code for ringing is applied. OPENING THE RING RELAY AT ZERO CURRENT The ring relay is automatically opened at zero current by the SLIC. The SLIC logic requires zero ringing current in the loop and either a valid switch hook detect (SHD) or a change in the operating mode (cadence of the ringing signal) to release the ring relay.
UniSLIC14 24 R1 50k INPUT FOR THE RING SYNC PULSE 5V 0V
Supervisory Functions
Switch Hook Detect Threshold
The Switch Hook Detect Threshold is programmed with a single external resistor (RD). The output of the SHD pin goes low when an off hook condition is detected.
Ground Key Detect Threshold
The Ground Key Detect Threshold is set internally and is not user programmable.
Ringing the Phone
The UniSLIC14 family handles all the popular ringing formats with high or low side ring trip detection. High side detection is possible because of the high common mode range on the ring signal detect input pins (DT, DR). To minimize power drain from the ring generator, when the phone is not being rung, the sense resistors are typically 2M. This reduces the current draw from the ring generator to just a few microamps. When the subscriber goes off hook during ringing, the UniSLIC14 family automatically releases the ring relay and DC feed is applied to the loop. The UniSLIC14 family has very low power dissipation in the on hook active mode. This enables the SLIC (during the ring cadence) to be powered up in the active state, avoiding unnecessary powering up and down of the SLIC. The control logic is designed to facilitate easy implementation of the ring cadence, requiring only one bit change to go from active to ringing and back again. DT, DR AND RRLY INPUTS Ring trip detection will occur when the DR pin goes more positive than DT by approximately 4V.
RSYNC_REV
FIGURE 18. REDUCING IMPULSE NOISE USING THE RSYNC_REV PIN AND SETTING THE POLARITY REVERSAL TIME
If the subscriber goes off hook during ringing, the SHD output will go low. An internal latch will sense SHD is low and disable the ring relay at zero ringing current. This prevents the ring signal from being reapplied to the line. To ring the line again, the SLIC must toggle between logic states. (Note: The previous state can not be the Reverse Active State. In the reverse state, the voltage on the CRT_REV_LVM
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capacitor will activate an internal latch prohibiting the ringing of the line. Figure 19 shows the sequence of events from ringing the phone to ring trip. The ring relay turns on when both the ringing code and ring sync pulse are present (A). SHD is high at this point. When the subscriber goes off hook the SHD pin goes low and stays low until the ringing control code is removed (B). This prevents the SHD output from pulsing after ring trip occurs. At the next zero current crossing of the ring signal, ring trip occurs and the ring relay releases the line to allow loop current to flow in the loop (C). active state (forward or reverse) and the subscriber is unaware the measurement is being taken.
RING GEN FREQ
TIP RING DR DT
UniSLIC14 GKD_LVM
PULSE WIDTH PROPORTIONAL TO LOOP LENGTH PULSE WIDTH LOOP LENGTH
RING GEN
RINGING VOLTAGE RING SYNC PULSE (A) RINGING CODE APPLIED SHD OUTPUT RINGING CURRENT IN LINE (C) RELAY DRIVER OFF ON OFF
FIGURE 20. OPERATION OF THE LINE VOLTAGE MEASUREMENT CIRCUIT
Polarity Reversal
(B)
Most of the SLICs in the UniSLIC14 family feature full polarity reversal. Full polarity reversal means that the SLIC can: transmit, determine the status of the line (on hook and off hook) and provide "silent" polarity reversal. The value of RSYNC_REV resistor is limited between 34.8k (10ms) and 73.2k (21ms). Reference Equation 39 to program the polarity reversal time.
FIGURE 19. RINGING SEQUENCE
Transhybrid Balance
If a low cost CODEC is chosen that does not have a transmit op-amp, the UniSLIC14 family of SLICs can solve this problem without the need for an additional op-amp. The solution is to use the Programmable Transmit Gain pin (PTG) as an input for the receive signal (VRX). In theory, when the PTG pin is connected to a divider network (R1 and R2 Figure 21) and the value of R1 and R2 is much less than the internal 500k resistors, two things happen. First the transmit gain from VRX to VTX is reduced by half. This is the result of shorting out the bottom 500k resistor with the much smaller external resistor. And second, the input signal from VRX is also decreased by the voltage divider R1 and R2. Transhybrid balance occurs when these two, equal but opposite in phase, signals are cancelled at the input to the output buffer. The calculation of the value of R2, once R1 is selected, is effected by the line feed resistors. EQ. 40 can be used to calculate the value of R2. Where : ZL= Line Impedance, ZTR = input impedance of SLIC including the protection resistor, and RP = protection resitors (typical 30).
* * R 1 II500K Z L + Z TR R 1 II500K R 2 = ------------------------- ----------------------------- - ------------------------1.02 Z L + 2ZR P 1.02
Operation of Line Voltage Measurement
A few of the SLICs in the UniSLIC14 family feature Line Voltage Measurement (LVM) capability. This feature provides a pulse on the GKD_LVM output pin that is proportional to the loop voltage. Knowing the loop voltage and thus the loop length, other basic cable characteristics such as attenuation and capacitance can be inferred. Decisions can be made about gain switching in the CODEC to overcome line losses and verification of the 2-wire circuit integrity. The LVM function can only be activated in the off hook condition in either the forward or reverse operating states. The LVM uses the ring signal supplied to the SLIC as a timebase generator. The loop resistance is determined by monitoring the pulse width of the output signal on the GKD_LVM pin. The output signal on the GKD_LVM pin is a square wave for which the average duration of the low state is proportional to the average voltage between the tip and ring terminals. The loop resistance is determined by the tip to ring voltage and the constant loop current. Reference Figure 20. Although the logic state changes to the Test Active State when performing this test, the SLIC is still powered up in the
(EQ. 40)
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+ A=1 VTX VTX + PTG R1 IX R2
network (including SLIC) to be tested up to the subscriber loop.
500K IX 500K
Pulse Metering
The HC55121, HC55142, HC35143, and HC55150 are designed to support pulse metering. They offer solutions to the following pulse metering design issues:
500K
VRX VRX +
500K 5 UniSLIC14
1) Providing adequate signal gain and current drive to the subscriber metering equipment to overcome the attenuation of this (12kHz, 16kHz) out of band signal. 2) Attenuating the pulse metering transhybrid signal without severely attenuating the voice band signal to avoid clipping in the CODEC/Filter. 3) Tailoring the overload levels in the SLIC to avoid clipping of the combined voiceband and pulse metering signal. 4) Having the provision of silent polarity reversal as a backup in the case where the loop attenuates the out of band signal too much for it to be detected by the subscriber's metering equipment.
FIGURE 21. TRANSHYBRID BALANCE USING THE PTG PIN
Loopback Tests
4-Wire Loopback Test
This feature can be very useful in the testing of line cards during the manufacturing process and in field use. The test is unobtrusive, allowing it to be used in live systems. Reference Figure 22. Most systems do not provide 4-wire loopback test capability because of costly relays needed to switch in external loads. All the SLICs in the UniSLIC14 family can easily provide this function when configured in the Open Circuit logic state. With the PTG pin floating, the signal on the VTX output is 180 out of phase and approximately 2 times the VRX input signal. If the PTG pin is grounded, then the amplitude will be approximately the same as the input signal and 180 out of phase.
Adequate Signal Gain
Adequate signal gain and current drive to the subscriber's metering equipment is made easier by the network shown in Figure 23. The pulse metering signal is supplied to a dedicated high impedance input pin called SPM. The circuit in Figure 23 shows the connection of a network that sets the 2-wire impedance (ZTR), at the pulse metering frequencies, to be approximately 200. If the line impedance (ZL) is equal to 200 at the pulse metering frequencies, then the 4-Wire to 2-wire gain (VTR/SPM) is equal 4. Thereby lowering the input signal requirements of the pulse metering signal. Note: The automatic pulse metering 2-wire impedance matching is independent of the programmed 2-wire impedance matching at voiceband frequencies. Calculation of the pulse metering gain is achieved by replacing VRX /500k in Equation 15 with SPM/125k and following the same process through to Equation 21. The UniSLIC14 sets the 2-wire input impedance of the SLIC (ZTR), including the protection resistors, equal to 200. The results are shown in Equation 41.
V TR ZL 200 A 4-2 = ------------- = - 8 ------------------------- = - 8 --------------------------- = - 4 SPM Z L + Z TR 200 + 200 (EQ. 41)
TIP
UniSLIC14 INTERNAL 600
VTX PTG VRX
+ DUAL SUPPLY CODEC/FILTER
RING
2-WIRE LOOPBACK
4-WIRE LOOPBACK
FIGURE 22. 4-WIRE AND 2-WIRE LOOPBACK TESTS
2-Wire Loopback Test
Most of the SLICs in the UniSLIC14 family feature 2-Wire loopback testing. This loopback function is only activated when the subscriber is on hook and the logic command to the SLIC is in the Test Active State. (Note: if the subscriber is off hook and in the Test Active State, the function performed is the Line Voltage Measurement.) During the 2-wire loopback test, a 2k internal resistor is switched across the tip and ring terminals of the SLIC. This allows the SHD function and the 4-wire to 4-wire AC transmission, right up to the subscriber loop, to be tested. Together with the 4-wire loopback test in the Open Circuit logic state, this 2-wire loopback test allows the complete
Avoiding Clipping in the CODEC/Filter
The amplitude of the returning pulse metering signal is often very large and could easily over drive the input to the CODEC/Filter. By using the same method discussed in section "Transhybrid Balance", most if not all of the pulse metering signal can be canceled out before it reaches the input to the CODEC/Filter. This connection is shown in Figure 23.
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Overload Levels and Silent Polarity Reversal
The pulse metering signal and voice are simultaneously transmitted, and therefore require additional overhead to prevent distortion of the signal. Reference section "Off hook Overhead Voltage" to account for the additional pulse metering signal requirements.
OUTPUT BUFFER RA 500K RB 500K + A=1 VTX VTX + PTG 30.1K R added to bottom of VSPM board 150pF C added to bottom of board Vttx + 500K + A=1 UniSLIC14 VRX VOUT
of the CODEC/Filter, one of the DC blocking capacitors can be eliminated (Figure 24B).
+ A=1
VTX
+ DUAL SUPPLY CODEC/FILTER
5V GND -5V
IX
FIGURE 24A.
IX
125K
VTX PTG
VIN VREF SINGLE SUPPLY DSP CODEC/FILTER VOUT
5
UniSLIC14
500K VRX UniSLIC14
FIGURE 23. PULSE METERING WITH TRANSHYBRID BALANCE
5V GND
Most of the SLICs in the UniSLIC14 family feature full polarity reversal. Full polarity reversal means that the SLIC can transmit, determine the status of the line (on hook and off hook) and provide "silent" polarity reversal. Reference Equation 39 to program the polarity reversal time.
FIGURE 24B. FIGURE 24. INTERFACE TO DUAL AND SINGLE SUPPLY CODECs
Interface to Dual and Single Supply CODECs
Great care has been taken to minimize the number of external components required with the UniSLIC14 family while still providing the maximum flexibility. Figures 24A, 24B) shows the connection of the UniSLIC14 to both a dual supply CODEC/Filter and a single supply DSP CODEC/Filter. To eliminate the DC blocking capacitors between the SLIC and the CODEC/Filter when using a dual supply CODEC/Filter, both the receive and transmit leads of the SLIC are referenced to ground. This leads to a very simple SLIC to CODEC/Filter interface, as shown in Figure 24A. When using a single supply DSP CODEC/Filter the output and input of the CODEC/Filter are no longer referenced to ground. To achieve maximum voltage swing with a single supply, both the output and input of the CODEC/Filter are referenced to its own VCC/2 reference. Thus, DC blocking capacitors are once again required. By using the PTG pin of the UniSLIC14 and the externally supplied VCC/2 reference
Power Management
The UniSLIC14 family provides two distinct power management capabilities: Power Sharing and Battery Selection
Power Sharing
Power sharing is a method of redistributing the power away from the SLIC in short loop applications. The total system power is the same, but the die temperature of the SLIC is much lower. Power sharing becomes important if the application has a single battery supply (-48V on hook requirements for faxes and modems) and the possibility of high loop currents (reference Figure 25). This technique would prevent the SLIC from getting too hot and thermally shutting down on short loops. The power dissipation in the SLIC is the sum of the smaller quiescent supply power and the much larger power that results from the loop current. The power that results from the loop current is the loop current times the voltage across the SLIC. The power sharing resistor (RPS) reduces the voltage across the SLIC, and thereby the on-chip power dissipation. The voltage across the SLIC is reduced by the voltage drop across RPS. This occurs because RPS is in series with the loop current and the negative supply. A mathematical verification follows:
25
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
Given: VBH = VBL = -48V, Loop current = 30mA, RL (load across tip and ring) = 600, Quiescent battery power = (48V) (0.8mA) = 38.4mW, Quiescent VCC power = (5V) (2.7mA) = 13.5mW, Power sharing resistor = 600. 1. Without power sharing, the on-chip power dissipation would be 952mW (Equation 42). 2. With power sharing, the on-chip power dissipation is 412mW (Equation 43). A power redistribution of 540mW. On-chip power dissipation without power sharing resistor.
PD = ( V BH ) ( 30mA ) + 38.4mW + 13.5mW - ( RL ) ( 30mA ) PD = 952mW
2
Battery Selection
Battery selection is a technique, for a two battery supply system, where the SLIC automatically diverts the loop current to the most appropriate supply for a given loop length. This results in significant power savings and lowers the total power consumption on short loops. This technique is particularly useful if most of the lines are short, and the on hook condition requires a -48V battery. In Figure 26, it can be seen that for long loops the majority of the current comes from the high battery supply (VBH) and for short loops from the low battery supply (VBL).
40 35 LOOP CURRENT (mA) 30 25 20 15 10 5 VBL 900 800 700 600 575 550 525 500 475 450 400 350 300 250 2000 1000 VBH 200 150 100 VBH VBL
(EQ. 42)
On-chip power dissipation with 600 power sharing resistor.
PD = ( V BH ) ( 30mA ) + 38.4mW + 13.5mW - ( R L ) ( 30mA ) - ( R PS ) ( 30mA ) PD = 412mW
2 2
(EQ. 43)
VBH = -48V VBL = -24V RILim = 33.2k
TIP RING ON SHORT LOOPS, THE MAJORITY OF CURRENT FLOWS OUT THE VBL PIN
UniSLIC14
VTX
0
VRX
LOOP RESISTANCE ()
FIGURE 26. BATTERY SELECTION (DUAL SUPPLY SYSTEMS)
VBL RPS VBH
-48V
-48V
FIGURE 25. POWER SHARING (SINGLE SUPPLY SYSTEMS)
Pinouts - 28 Lead PLCC Packages
HC55120 (28 LEAD PLCC) TOP VIEW
RRLY VRX PTG VTX CH NC ZT ZT
HC55121 (28 LEAD PLCC) TOP VIEW
RRLY SPM 27 VRX 26 PTG 1 VTX 28 CH 3
4
3
2
1
28
27
26
4
2
RING 5 BGND 6 TIP 7 VBH 8 VBL 9 RDC_RAC 10 CRT 11
25 AGND 24 RSYNC 23 ILIM 22 ROH 21 RD 20 VCC 19 GKD
RING 5 BGND 6 TIP 7 VBH 8 VBL 9 RDC_RAC 10 CRT_REV 11
25 AGND 24 RSYNC_REV 23 ILIM 22 ROH 21 RD 20 VCC 19 GKD
12 CDC
13 DT
14 DR
15 C3
16 C2
17 C1
18 SHD
12 CDC
13 DT
14 DR
15 C3
16 C2
17 C1
18 SHD
26
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Pinouts - 28 Lead PLCC Packages
HC55130 (28 LEAD PLCC) TOP VIEW
RRLY VRX PTG VTX CH CH NC ZT ZT
(Continued) HC55140 (28 LEAD PLCC) TOP VIEW
RRLY VRX 26 PTG VTX 28 NC 27
4
3
2
1
28
27
26
4
3
2
1
RING 5 BGND 6 TIP 7 VBH 8 VBL 9 RDC_RAC 10 CRT 11
25 AGND 24 RSYNC 23 ILIM 22 ROH 21 RD 20 VCC 19 NC
RING 5 BGND 6 TIP 7 VBH 8 VBL 9 RDC_RAC 10 CRT_REV_ 11 LVM 12 CDC 13 DT 14 DR 15 C3 16 C2 17 C1 18 SHD
25 AGND 24 RSYNC_REV 23 ILIM 22 ROH 21 RD 20 VCC 19 GKD_LVM
12 CDC
13 DT
14 DR
15 C3
16 C2
17 C1
18 SHD
HC55142 (28 LEAD PLCC) TOP VIEW
RRLY SPM VRX PTG VTX CH CH ZT ZT
HC55150 (28 LEAD PLCC) TOP VIEW
RRLY SPM 27 VRX 26 PTG 1 VTX 28
4
3
2
1
28
27
26
4
3
2
RING BGND TIP VBH VBL
5 6 7 8 9
25 AGND 24 RSYNC_REV 23 ILIM 22 ROH 21 RD 20 VCC 19 GKD_LVM
RING 5 BGND 6 TIP 7 VBH 8 VBL 9 RDC_RAC 10 CRT_REV_ 11 LVM 12 CDC 13 DT 14 DR 15 C3 16 C2 17 C1 18 SHD
25 AGND 24 RSYNC_REV 23 ILIM 22 ROH 21 RD 20 VCC 19 LVM
RDC_RAC 10 CRT_REV_ 11 LVM 12 CDC 13 DT 14 DR 15 C3 16 C2 17 C1 18 SHD
27
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Pinouts - 32 Lead PLCC Packages
HC55143 (32 LEAD PLCC) TOP VIEW
TRLY1 TRLY2 31 RRLY PTG VTX 30 29 SPM 28 VRX 27 AGND 26 RSYNC_REV 25 ILIM 24 ROH 23 RD 22 VCC 21 GKD_LVM 14 DR 15 C5 16 C4 17 C3 18 C2 19 C1 20 SHD
4 RING 5 BGND 6 TIP 7 VBH VBL 8 9
CH 3
ZT
2
1
32
RDC_RAC 10 CRT_REV_ 11 LVM CDC 12 DT 13
Pinouts - 28 Lead SOIC Packages
HC55120 (28 LEAD SOIC) TOP VIEW
ZT 1 PTG 2 RRLY 3 CH 4 RING 5 BGND 6 TIP 7 VBH 8 VBL 9 RDC_RAC 10 CDC 11 DT 12 DR 13 CRT 14 28 AGND 27 VTX 26 NC 25 VRX 24 RSYNC 23 ILIM 22 ROH 21 RD 20 VCC 19 SHD 18 C1 17 C2 16 C3 15 GKD ZT 1 PTG 2 RRLY 3 CH 4 RING 5 BGND 6 TIP 7 VBH 8 VBL 9 RDC_RAC 10 CDC 11 DT 12 DR 13 CRT_REV 14
HC55121 (28 LEAD SOIC) TOP VIEW
28 AGND 27 VTX 26 SPM 25 VRX 24 RSYNC_REV 23 ILIM 22 ROH 21 RD 20 VCC 19 SHD 18 C1 17 C2 16 C3 15 GKD
28
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Pinouts - 28 Lead SOIC Packages
HC55130 (28 LEAD SOIC) TOP VIEW
ZT 1 PTG 2 RRLY 3 CH 4 RING 5 BGND 6 TIP 7 VBH 8 VBL 9 RDC_RAC 10 CDC 11 DT 12 DR 13 CRT 14 28 AGND 27 VTX 26 NC 25 VRX 24 RSYNC 23 ILIM 22 ROH 21 RD 20 VCC 19 SHD 18 C1 17 C2 16 C3 15 NC ZT 1 PTG 2 RRLY 3 CH 4 RING 5 BGND 6 TIP 7 VBH 8 VBL 9 RDC_RAC 10 CDC 11 DT 12 DR 13 CRT_REV_LVM 14
(Continued) HC55140 (28 LEAD SOIC) TOP VIEW
28 AGND 27 VTX 26 NC 25 VRX 24 RSYNC_REV 23 ILIM 22 ROH 21 RD 20 VCC 19 SHD 18 C1 17 C2 16 C3 15 GKD_LVM
HC55142 (28 LEAD SOIC) TOP VIEW
ZT 1 PTG 2 RRLY 3 CH 4 RING 5 BGND 6 TIP 7 VBH 8 VBL 9 RDC_RAC 10 CDC 11 DT 12 DR 13 CRT_REV_LVM 14 28 AGND 27 VTX 26 SPM 25 VRX 24 RSYNC_REV 23 ILIM 22 ROH 21 RD 20 VCC 19 SHD 18 C1 17 C2 16 C3 15 GKD_LVM ZT 1 PTG 2 RRLY 3 CH 4 RING 5 BGND 6 TIP 7 VBH 8 VBL 9 RDC_RAC 10 CDC 11 DT 12 DR 13 CRT_REV_LVM 14
HC55150 (28 LEAD SOIC) TOP VIEW
28 AGND 27 VTX 26 SPM 25 VRX 24 RSYNC_REV 23 ILIM 22 ROH 21 RD 20 VCC 19 SHD 18 C1 17 C2 16 C3 15 LVM
Pin Descriptions
28 PIN PLCC 1 32 PIN PLCC 1 28 PIN SOIC 2 SYMBOL PTG DESCRIPTION Programmable Transmit Gain - The 2-wire to 4-wire transmission gain is 0dB if this pin is left floating and -6.02dB if tied to ground. The -6.02dB gain option is useful in systems where Pulse Metering is used. See Figure 23. Ring Relay Driver Output - The relay coil may be connected to a maximum of 14V. AC/DC Separation Capacitor - CH is required to properly process the AC current from the DC loop current. Recommended value 0.1F. 2-Wire Impedance Matching Pin - Impedance matching of the 2-wire side is accomplished by placing an impedance between the ZT pin and ground. See Equation 32. Connects via protection resistor RP to ring wire of subscriber pair. Battery ground. Connects via protection resistor RP to tip wire of subscriber pair.
FN4659.13 June 1, 2006
2 3 4 5 6 7
2 3 4 5 6 7
3 4 1 5 6 7
RRLY CH ZT RING BGND TIP
29
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Pin Descriptions
28 PIN PLCC 8 9 10 11 32 PIN PLCC 8 9 10 11 28 PIN SOIC 8 9 10 14 (Continued)
SYMBOL VBH VBL RDC_RAC CRT_REV _LVM
DESCRIPTION High Battery Supply (negative with respect to GND). Low Battery Supply (negative with respect to GND, magnitude VBH). Resistive Feed/Anti Clipping - Performs anti clipping function on constant current application and sets the slope of the resistive feed curve for constant voltage applications. Ring Trip, Soft Polarity Reversal and Line Voltage Measurement - A capacitor when placed between the CRT_REV_LVM pin and +5V performs 3 mutually exclusive functions. When the SLIC is configured in the Ringing mode it provides filtering of the ringing signal to prevent false detect. When the SLIC is transitioning between the Forward Active State and Reverse Active State it provides Soft Polarity Reversal and performs charge storage in the Line Voltage Measurement State. Recommended value 0.47F. Filter Capacitor - The CDC Capacitor removes the VF signals from the battery feed control loop. Tip side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external network to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DT is more negative than the voltage on DR. Ring Side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external network to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DR is more positive than the voltage on DT. Activates Test Relay TRLY2. TTL Compatible Logic Input. C5 input high, test relay TRLT2 Low(ON). C5 input floating, test relay TRLY2 High(OFF). This is due to an internal 100k pull down resistor. Activates Test Relay TRLY1. TTL Compatible Logic Input. C4 input high, test relay TRLT1 Low(ON). C4 input floating, test relay TRLY1 High(OFF). This is due to an internal 100k pull down resistor. TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the SLIC. Reference Table 1 for details. TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the SLIC. Reference Table 1 for details. TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the SLIC. Reference Table 1 for details. Switch Hook Detect - Active during off hook, ground key and loopback. Reference Table 1 for details. Ground Key Detector and Line Voltage Measurement - Reference Table 1 for details. 5V Supply. Loop Current Threshold Programming Pin - A resistor between this pin and ground will determine the trigger level for the loop current detect circuit. See Equation 7. Off Hook Overload Setting Resistor - Used to set combined overhead for voice and pulse metering signals. See Equation 10. Current Limit Programming Pin - A resistor between this pin and ground will determine the constant current limit of the feed curve. See Equation 11. Ring Synchronization Input and Reversal Time Setting. A resistor between this pin and GND determines the polarity reversal time. Synchronization of the closing of the relay at zero voltage is achieved via a ring sync pulse (5V to 0V) synchronized to the ring signal zero voltage crossing (Reference Figure 18). Analog ground Receive Input - Ground referenced 4-wire side. Pulse Metering Signal Input. If pulse metering is not used, then this pin should be grounded as close to the device pin as possible. Input impedance to ground = 125k. Transmit Output - Ground referenced 4-wire side. Test Relay Driver 2. Open Collector Transistor. Internal Clamp between it's output and ground elimnates the need to place an external snubber diode across Test Relay Driver. TRLY2 may be connected to maximum of 14V. Test Relay Driver 1. Open Collector Transistor. Internal Clamp between it's output and ground elimnates the need to place an external snubber diode across Test Relay Driver. TRLY1 may be connected to maximum of 14V.
12 13
12 13
11 12
CDC DT
14
14
13
DR
15 16 17 18 19 20 21 22 23 24
15 16 17 18 19 20 21 22 23 24 25 26
16 17 18 19 15 20 21 22 23 24
C5 C4 C3 C2 C1 SHD GKD_LVM VCC RD ROH ILIM RSYNC_REV
25 26 27 28 -
27 28 29 30 31
28 25 26 27 -
AGND VRX SPM VTX TRLY2
-
32
-
TRLY1
30
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Basic Application Circuit - Voice Only 28 Lead PLCC Package
R11
+5V +5V OR +12V RELAY
20 C1 2 3 RP U2 C2 C8 5 6
VCC RRLY CH RING BGND
U1
VTX PTG SPM VRX AGND ZT
28 1 27 26 25 4 24 23 22 21 18 19 17 16 15 R8 R7 R6 R5 R4
C10
R9
RING
C11
R10
CODEC/FILTER
TIP
RP D1
C9
7 8
TIP VBH VBL RDC_RAC CDC DT DR
RSYNC_REV ILIM ROH RD SHD GKD_LVM C1 C2 C3
PERFORM TRANSHYBRID BALANCE WHEN USING A NON-DSP CODEC. NOT REQUIRED FOR DSP CODEC. NOT REQUIRED FOR NON-DSP CODEC's. REQUIRED FOR DSP CODEC's
-24V -48V C5 C6
OPTIONAL
C7 R1 +
9 10 - 12 13 14
R2 R12 R3 RING GENERATOR
VBAT
C3
11 C4 +5V
CRT_REV_LVM
CONTROL LOGIC
FIGURE 27. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST COMPONENT U1 - SLIC U2 - Dual Asymmetrical Transient Voltage Suppressor RP (Line Feed Resistors) R1 (RDC_RAC Resistor) R2, R3 R4 (RD Resistor) R5 (ROH Resistor) R6 (RILIM Resistor) R7 (RSYNC_REV Resistor) R8 (RZT Resistor) R9, R10, R11 R12 C1 (Supply Decoupling), C2 C5 (Supply Decoupling) C6 (Supply Decoupling) C4, C7, C10, C11 C3 C8, C9 D1, Recommended if the VBL supply is not derived from the VBH Supply VALUE UniSLIC14 Family TISP1072F3 30 21k 2M 41.2k 38.3k 33.2k 34.8k 107k 20k 400 0.1F 0.1F 0.1F 0.47F 4.7F 2200pF 1N4004 TOLERANCE N/A N/A Matched 1% 1% 1% 1% 1% 1% 1% 1% 1% 5% 20% 20% 20% 20% 20% 20% RATING N/A N/A 2.0W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2W 10V 50V 100V 10V 50V 100V -
Design Parameters: Maximum on hook voltage = 0.775VRMS, Maximum Off hook Voice = 3.2VPEAK, Switch Hook Threshold = 12mA, Loop Current Limit = 31mA, Synthesize Device Impedance = 540 (600 - 60), with 30 protection resistors, impedance across Tip and Ring terminals = 600. Where applicable, these component values apply to the Basic Application Circuits for the HC55120, HC55121, HC55130/1, HC55140/1, HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.
31
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Basic Application Circuit - Pulse Metering 28 Lead PLCC Package
+5V +5V OR +12V RELAY
R11 20 VCC RRLY CH RING BGND U1 VTX PTG SPM VRX AGND ZT 28 1 27 26 25 4 24 23 22 21 18 19 17 16 15
CONTROL LOGIC
C10
R9
C1
2 3
RING
RP U2
C2 C8
5 6
C11
R10
R8 R7 R6 R5 R4
CODEC/FILTER
TIP -24V -48V C5 C6
RP D1 OPTIONAL
C9
7 8 C7 R1 9 10 - 12 C3 13 14
TIP VBH VBL RDC_RAC CDC DT DR
RSYNC_REV ILIM ROH RD SHD GKD_LVM C1 C2 C3
12/16kHz PULSE METERING INPUT SIGNAL
PERFORM TRANSHYBRID BALANCE WHEN USING A NON-DSP CODEC. NOT REQUIRED FOR DSP CODEC.
+ R2 RING GENERATOR VBAT R12 R3
NOT REQUIRED FOR NON-DSP CODEC's. REQUIRED FOR DSP CODEC's
11 C4 +5V
CRT_REV_LVM
FIGURE 28. UniSLIC14 PULSE METERING BASIC APPLICATION CIRCUIT TABLE 3. BASIC APPLICATION CIRCUIT COMPONENT LIST COMPONENT U1 - SLIC U2 - Dual Asymmetrical Transient Voltage Suppressor RP (Line Feed Resistors) R1 (RDC_RAC Resistor) R2, R3 R4 (RD Resistor) R5 (ROH Resistor) R6 (RILIM Resistor) R7 (RSYNC_REV Resistor) R8 (RZT Resistor) R9, R10, R11 R12 C1 (Supply Decoupling), C2 C5 (Supply Decoupling) C6 (Supply Decoupling) C4, C7, C10, C11 C3 C8, C9 D1, Recommended if the VBL supply is not derived from the VBH Supply VALUE UniSLIC14 Family TISP1072F3 30 26.1k 2M 41.2k 38.3k 33.2k 34.8k 107k 20k 400 0.1F 0.1F 0.1F 0.47F 4.7F 2200pF 1N4004 TOLERANCE N/A N/A Matched 1% 1% 1% 1% 1% 1% 1% 1% 1% 5% 20% 20% 20% 20% 20% 20% RATING N/A N/A 2.0W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2W 10V 50V 100V 10V 50V 100V -
Design Parameters: Maximum on hook voltage = 0.775VRMS, Maximum off hook voice = 1.1VPEAK, Maximum simultaneous pulse metering signal = 2.2VRMS, Switch Hook Threshold = 12mA, Loop Current Limit = 31mA, Synthesize Device Impedance = 540 (600 - 60), with 30 protection resistors, impedance across Tip and Ring terminals = 600 . Where applicable, these component values apply to the Basic Application Circuits for the HC55120, HC55121, HC55130/1, HC55140/1, HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.
32
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Basic Application Circuit - Voice Only 28 Lead SOIC Package
+5V +5V OR +12V RELAY
R11 20 27
C1
VCC RRLY CH RING BGND
C10
U1
R9
3 4
VTX
RING
RP U2
C2 C8
SPM VRX AGND ZT
26 25 28 1 24 23 22 21 19 15 18 17 16 R8 R7 R6 R5 R4
5 6
C11
R10
CODEC/FILTER
TIP
RP D1
C9
7 8
TIP VBH VBL RDC_RAC CDC DT DR
RSYNC_REV ILIM ROH RD SHD GKD_LVM C1 C2 C3
PERFORM TRANSHYBRID BALANCE WHEN USING A NON-DSP CODEC. NOT REQUIRED FOR DSP CODEC. NOT REQUIRED FOR NON-DSP CODEC's. REQUIRED FOR DSP CODEC's
-24V -48V C5 C6
OPTIONAL
C7 R1 + C3
9 10 11 12 13
R2 R12 R3 RING GENERATOR VBAT
14 C4 +5V
CRT_REV_LVM
CONTROL LOGIC
FIGURE 29. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT TABLE 4. BASIC APPLICATION CIRCUIT COMPONENT LIST COMPONENT U1 - SLIC U2 - Dual Asymmetrical Transient Voltage Suppressor RP (Line Feed Resistors) R1 (RDC_RAC Resistor) R2, R3 R4 (RD Resistor) R5 (ROH Resistor) R6 (RILIM Resistor) R7 (RSYNC_REV Resistor) R8 (RZT Resistor) R9, R10, R11 R12 C1 (Supply Decoupling), C2 C5 (Supply Decoupling) C6 (Supply Decoupling) C4, C7, C10, C11 C3 C8, C9 D1, Recommended if the VBL supply is not derived from the VBH Supply VALUE UniSLIC14 Family TISP1072F3 30 21k 2M 41.2k 38.3k 33.2k 34.8k 107k 20k 400 0.1F 0.1F 0.1F 0.47F 4.7F 2200pF 1N4004 TOLERANCE N/A N/A Matched 1% 1% 1% 1% 1% 1% 1% 1% 1% 5% 20% 20% 20% 20% 20% 20% RATING N/A N/A 2.0W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 2W 10V 50V 100V 10V 50V 100V -
Design Parameters: Maximum on hook voltage = 0.775VRMS, Maximum Off hook Voice = 3.2VPEAK, Switch Hook Threshold = 12mA, Loop Current Limit = 31mA, Synthesize Device Impedance = 540 (600 - 60), with 30 protection resistors, impedance across Tip and Ring terminals = 600. Where applicable, these component values apply to the Basic Application Circuits for the HC55120, HC55121, HC55130/1, HC55140/1, HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.
33
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 10.00 0.25 0.40 28 0o MAX 2.65 0.30 0.51 0.32 18.10 7.60 10.65 0.75 1.27 8o NOTES 9 3 4 5 6 7 Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 0.394 0.01 0.016 28 0o
MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 0.419 0.029 0.050 8o
B C D E
A1 0.10(0.004) C
e H h L N
0.05 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
34
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP 0.004 (0.10) C
N28.45 (JEDEC MS-018AB ISSUE A)
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A MIN 0.165 0.090 0.485 0.450 0.191 0.485 0.450 0.191 28 MAX 0.180 0.120 0.495 0.456 0.219 0.495 0.456 0.219 MILLIMETERS MIN 4.20 2.29 12.32 11.43 4.86 12.32 11.43 4.86 28 MAX 4.57 3.04 12.57 11.58 5.56 12.57 11.58 5.56 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97
0.025 (0.64) R 0.045 (1.14)
D2/E2 E1 E C L
A1 D D1
D2/E2 VIEW "A"
D2 E E1
D1 D 0.020 (0.51) MAX 3 PLCS
A1 A
0.020 (0.51) MIN
E2 N
SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14) MIN VIEW "A" TYP.
0.025 (0.64) MIN
NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions.
35
FN4659.13 June 1, 2006
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP ND 0.004 (0.10) C
N32.45x55 (JEDEC MS-016AE ISSUE A)
32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A MIN 0.125 0.060 0.485 0.447 0.188 0.585 0.547 0.238 28 7 9 MAX 0.140 0.095 0.495 0.453 0.223 0.595 0.553 0.273 MILLIMETERS MIN 3.18 1.53 12.32 11.36 4.78 14.86 13.90 6.05 28 7 9 MAX 3.55 2.41 12.57 11.50 5.66 15.11 14.04 6.93 NOTES 3 4, 5 3 4, 5 6 7 7 Rev. 0 7/98 NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions. 7. ND denotes the number of leads on the two shorts sides of the package, one of which contains pin #1. NE denotes the number of leads on the two long sides of the package.
0.025 (0.64) R 0.045 (1.14)
D2/E2 C L D2/E2 NE VIEW "A"
A1 D
E1 E
D1 D2 E E1 E2
A1 A 0.015 (0.38) MIN
N ND NE
D1 D 0.020 (0.51) MAX 3 PLCS 0.050 (1.27) MIN
SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81)
0.025 (0.64) MIN
0.013 (0.33) 0.021 (0.53) (0.12) M A S -B S D S 0.005 VIEW "A" TYP.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 36
FN4659.13 June 1, 2006

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